85 lines
2.6 KiB
C
85 lines
2.6 KiB
C
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#ifndef __MCU_FLASH_H
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#define __MCU_FLASH_H
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#define XRAM_MAP_ADDR 0x0000
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#define MCUFLASH_BK1_ADDR 0x0000
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#define MCUFLASH_BK2_ADDR (MCUFLASH_BK1_ADDR + 512)
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#define MCUFLASH_BK1_FLG_ADDR (MCUFLASH_BK1_ADDR + 510)
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#define MCUFLASH_BK2_FLG_ADDR (MCUFLASH_BK2_ADDR + 510)
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#define MCUFLASH_SECTOR_SIZE 512 //1Sector<6F>ij<EFBFBD><C4B3><EFBFBD>Ϊ512<31>ֽ<EFBFBD>
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#define MCU_FLASH_WATI_DELAY 2
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/**************************************************************************************/
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//MCU Flash<73><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>
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/**************************************************************************************/
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//ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʼ SubClassID=0x00
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#define SYS_PARA_MAP_ADDR XRAM_MAP_ADDR
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#define SYS_PARA_LEN 48
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//<2F>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x01
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#define SYSINFO_MAP_ADDR (SYS_PARA_MAP_ADDR+SYS_PARA_LEN)
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#define SYSINFO_LEN 50
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x02
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#define CHG_PARA_MAP_ADDR (SYSINFO_MAP_ADDR+SYSINFO_LEN)
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#define CHG_PARA_LEN 18
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//<2F>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x03
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#define DSG_PARA_MAP_ADDR (CHG_PARA_MAP_ADDR+CHG_PARA_LEN)
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#define DSG_PARA_LEN 21
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//Ԥ<><D4A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x04
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//Reserved
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//<2F>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x05
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#define DSG_PWM_PARA_MAP_ADDR (DSG_PARA_MAP_ADDR+DSG_PARA_LEN)
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#define DSG_PWM_PARA_LEN 5
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//<2F><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x06
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#define CHG_TEMP_PARA_MAP_ADDR (DSG_PWM_PARA_MAP_ADDR+DSG_PWM_PARA_LEN)
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#define CHG_TEMP_PARA_LEN 11
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//<2F>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x07
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#define DSG_TEMP_PARA_MAP_ADDR (CHG_TEMP_PARA_MAP_ADDR+CHG_TEMP_PARA_LEN)
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#define DSG_TEMP_PARA_LEN 9
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//ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x08
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#define BAL_PARA_MAP_ADDR (DSG_TEMP_PARA_MAP_ADDR+DSG_TEMP_PARA_LEN)
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#define BAL_PARA_LEN 8
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//<2F><><EFBFBD><EFBFBD>ͳ<EFBFBD>Ʋ<EFBFBD><C6B2><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x09
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#define SOC_PARA_MAP_ADDR (BAL_PARA_MAP_ADDR+BAL_PARA_LEN)
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#define SOC_PARA_LEN 17
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//AFE<46><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0A
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#define AFE_PARA_MAP_ADDR (SOC_PARA_MAP_ADDR+SOC_PARA_LEN)
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#define AFE_PARA_LEN 4
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//У<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0B
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#define CALI_PARA_MAP_ADDR (AFE_PARA_MAP_ADDR+AFE_PARA_LEN)
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#define CALI_PARA_LEN 12
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#define RESERVED_DATA_MAP_ADDR (CALI_PARA_MAP_ADDR+CALI_PARA_LEN)
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#define RESERVED_DATA_LEN (510-(RESERVED_DATA_MAP_ADDR))
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#define DataflashCheck_Map_ADDR 0xfe
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#define DataflashCheck_LEN 0x0002
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extern BOOL bMcuFlashWrWaitFlg;
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extern BOOL bMcuFlashWrFlg;
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extern BOOL bMcuFlashErr;
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extern U8 xdata ucMcuFlashWrValid;
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extern U8 xdata bMcuFlashWrWaitCnt;
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extern BOOL McuFlashRead(U16 SourceAddr, U8 xdata *TargetAddr, U16 Length);
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extern BOOL McuFlashWrite(U16 McuFlashAddr, U16 XramAddr);
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extern void McuFlashWrOneByte(U16 McuFlashAddr,U8 WrData);
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extern void McuFlashProcess(void);
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extern void McuFlashWrWaitCheck(void);
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extern BOOL McuFlashCheckFlg(U16 Saddr);
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#endif
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