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ZDBMS/output/Memory.lst

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修改均衡起始电压为50mv
2025-02-19 06:13:28 +00:00
C51 COMPILER V9.01 MEMORY 02/19/2025 10:42:27 PAGE 1
First commit
2025-02-06 07:35:32 +00:00
C51 COMPILER V9.01, COMPILATION OF MODULE MEMORY
OBJECT MODULE PLACED IN .\output\Memory.obj
COMPILER INVOKED BY: D:\Tool\Keil\C51\BIN\C51.EXE code_app\Memory.c LARGE OPTIMIZE(7,SIZE) REGFILE(.\output\MCUCore_Load
-.ORC) BROWSE INTVECTOR(0X1000) INCDIR(.\header_app;.\header_drv;.\code_gasguage;.\code_classb\iec60730_lib\include;.\cod
-e_classb\iec60730_proc\Include;.\code_classb\config) DEBUG OBJECTEXTEND PRINT(.\output\Memory.lst) OBJECT(.\output\Memor
-y.obj)
line level source
1 /********************************************************************************
2 Copyright (C), Sinowealth Electronic. Ltd.
3 Author: Sino
4 Version: V0.0
5 Date: 2020/04/26
6 History:
7 V2.0 2020/04/26 Preliminary
8 ********************************************************************************/
9 #include "Main.h"
10
11
12 //*****************************DATA MEMORY START***************************//
13 U8 idata STACK[0x100-STACK_ADDR] _at_ STACK_ADDR; //<2F><>ջ
14
15 //*****************************BIT MEMORY START***************************//
16 U16 bdata uiPackConfig;
17 sbit bCellNum1 = uiPackConfig^8;
18 sbit bCellNum2 = uiPackConfig^9;
19 sbit bCellNum3 = uiPackConfig^10;
20 sbit bLEDNum0 = uiPackConfig^11; //Ԥ<><D4A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9>
21 sbit bLEDNum1 = uiPackConfig^12;
22 sbit bTempNum = uiPackConfig^13;
23 sbit bChgerLock = uiPackConfig^14; //<2F>Ƿ<EFBFBD>֧<EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
24 sbit bLoadLock = uiPackConfig^15; //<2F>Ƿ<EFBFBD>֧<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
25
26 sbit bSC_EN = uiPackConfig^0; //00101011
27 sbit bOV_EN = uiPackConfig^1;
28 sbit bOCRC_EN = uiPackConfig^2; //auto reset or nor when OCC
29 sbit bBAL_EN = uiPackConfig^3;
30 sbit bPF_EN = uiPackConfig^4; //disable
31 sbit bCTO_EN = uiPackConfig^5; //cell on
32 sbit bOCPM = uiPackConfig^6; //disable
33 sbit bEnEEPRomBK = uiPackConfig^7;
34
35 U16 bdata uiPackStatus;
36 sbit bCHGMOS = uiPackStatus^8;
37 sbit bDSGMOS = uiPackStatus^9;
38 sbit bCHGING = uiPackStatus^10;
39 sbit bDSGING = uiPackStatus^11;
40 sbit bSlowDischarge = uiPackStatus^12;
41 sbit bMidDischarge = uiPackStatus^13;
42 sbit bFastDischarge = uiPackStatus^14;
43
44 sbit bFC = uiPackStatus^0;
45 sbit bFD = uiPackStatus^1;
46 sbit bVDQ = uiPackStatus^2;
47
48
49 U16 bdata uiBatStatus;
50 sbit bOV = uiBatStatus^8;
51 sbit bUV = uiBatStatus^9;
52 sbit bOCC = uiBatStatus^10;
修改均衡起始电压为50mv
2025-02-19 06:13:28 +00:00
C51 COMPILER V9.01 MEMORY 02/19/2025 10:42:27 PAGE 2
First commit
2025-02-06 07:35:32 +00:00
53 sbit bOCD1 = uiBatStatus^11;
54 sbit bOCD2 = uiBatStatus^12;
55
56 sbit bOTC = uiBatStatus^0;
57 sbit bOTD = uiBatStatus^1;
58 sbit bUTC = uiBatStatus^2;
59 sbit bUTD = uiBatStatus^3;
60 sbit bAFE_OV = uiBatStatus^4;
61 sbit bAFE_SC = uiBatStatus^5;
62 sbit bCTO = uiBatStatus^6;
63
64 U8 bdata ucAFEStatus;
65 sbit bAfeChger = ucAFEStatus^0;
66 sbit bAfeLoad = ucAFEStatus^1;
67 sbit bAfeChging = ucAFEStatus^2;
68 sbit bAfeDsging = ucAFEStatus^3;
69 sbit bAfeCHG = ucAFEStatus^4;
70 sbit bAfeDSG = ucAFEStatus^5;
71
72 /**************************************************************************************/
73 //DataFlash<73><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>
74 /**************************************************************************************/
75 //ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʼ SubClassID=0x00 langth=48
76 U16 xdata E2uiPackConfigMap _at_ SYS_PARA_MAP_ADDR;
77 U16 xdata E2uiVOC[10] _at_ SYS_PARA_MAP_ADDR+2;
78 U32 xdata E2ulDesignCapacity _at_ SYS_PARA_MAP_ADDR+22;
79 U32 xdata E2ulFCC _at_ SYS_PARA_MAP_ADDR+26;
80 U32 xdata E2ulCycleThreshold _at_ SYS_PARA_MAP_ADDR+30;
81 U16 xdata E2uiCycleCount _at_ SYS_PARA_MAP_ADDR+34;
82 U16 xdata E2uiLearnLowTempe _at_ SYS_PARA_MAP_ADDR+36;
83 U16 xdata E2Reserve _at_ SYS_PARA_MAP_ADDR+38;//<2F><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>Ԥ<EFBFBD><D4A4>ռλ
84 S16 xdata E2siDfilterCur _at_ SYS_PARA_MAP_ADDR+40;
85 U8 xdata E2ucLowPowerDeley _at_ SYS_PARA_MAP_ADDR+42;
86 U8 xdata E2ucChgBKDelay _at_ SYS_PARA_MAP_ADDR+43;
87 S16 xdata E2siChgBKCur _at_ SYS_PARA_MAP_ADDR+44;
88 U8 xdata E2ucRTCBKDelay _at_ SYS_PARA_MAP_ADDR+46;
89 U8 xdata E2ucRamCheckFlg0 _at_ SYS_PARA_MAP_ADDR+47; //ucRamCheckFlg + SubClassID
90
91 //<2F>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x01 langth=50
92 U16 xdata E2uiSWVersion _at_ SYSINFO_MAP_ADDR;
93 U16 xdata E2uiHWVersion _at_ SYSINFO_MAP_ADDR+2;
94 U8 xdata E2ucID _at_ SYSINFO_MAP_ADDR+4;
95 U8 xdata E2ucMNFName[12] _at_ SYSINFO_MAP_ADDR+5;
96 U32 xdata E2ulMNFDate _at_ SYSINFO_MAP_ADDR+17;
97 U16 xdata E2uiSerialNum _at_ SYSINFO_MAP_ADDR+21;
98 U8 xdata E2ucDeviceName[12] _at_ SYSINFO_MAP_ADDR+23;
99 U8 xdata E2ucDeviceChem[12] _at_ SYSINFO_MAP_ADDR+35;
100 U16 xdata E2uiChemID _at_ SYSINFO_MAP_ADDR+47;
101 U8 xdata E2ucRamCheckFlg1 _at_ SYSINFO_MAP_ADDR+49;
102
103 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x02 langth=18
104 U16 xdata E2uiOVvol _at_ CHG_PARA_MAP_ADDR;
105 U16 xdata E2uiOVRvol _at_ CHG_PARA_MAP_ADDR+2;
106 U8 xdata E2ucOVDelay _at_ CHG_PARA_MAP_ADDR+4;
107 U8 xdata E2ucOVRDelay _at_ CHG_PARA_MAP_ADDR+5;
108 U16 xdata E2uiChgEndVol _at_ CHG_PARA_MAP_ADDR+6;
109 S16 xdata E2siChgEndCurr _at_ CHG_PARA_MAP_ADDR+8;
110 U8 xdata E2ucChgEndDelay _at_ CHG_PARA_MAP_ADDR+10;
111 S32 xdata E2slOCCCurrent _at_ CHG_PARA_MAP_ADDR+11;
112 U8 xdata E2ucOCCDelay _at_ CHG_PARA_MAP_ADDR+15;
113 U8 xdata E2ucOCCRDelay _at_ CHG_PARA_MAP_ADDR+16;
114 U8 xdata E2ucRamCheckFlg2 _at_ CHG_PARA_MAP_ADDR+17;
修改均衡起始电压为50mv
2025-02-19 06:13:28 +00:00
C51 COMPILER V9.01 MEMORY 02/19/2025 10:42:27 PAGE 3
First commit
2025-02-06 07:35:32 +00:00
115
116 //<2F>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x03 langth=21
117 U16 xdata E2uiUVvol _at_ DSG_PARA_MAP_ADDR;
118 U16 xdata E2uiUVRvol _at_ DSG_PARA_MAP_ADDR+2;
119 U8 xdata E2ucUVDelay _at_ DSG_PARA_MAP_ADDR+4; //all the delay unit is 500mS
120 U8 xdata E2ucUVRDelay _at_ DSG_PARA_MAP_ADDR+5;
121 U16 xdata E2uiDsgEndVol _at_ DSG_PARA_MAP_ADDR+6;
122 U8 xdata E2ucDsgEndDelay _at_ DSG_PARA_MAP_ADDR+8;
123 S32 xdata E2slOCD1Current _at_ DSG_PARA_MAP_ADDR+9;
124 U8 xdata E2ucOCD1Delay _at_ DSG_PARA_MAP_ADDR+13;
125 S32 xdata E2slOCD2Current _at_ DSG_PARA_MAP_ADDR+14;
126 U8 xdata E2ucOCD2Delay _at_ DSG_PARA_MAP_ADDR+18;
127 U8 xdata E2ucLoadRDelay _at_ DSG_PARA_MAP_ADDR+19;
128 U8 xdata E2ucRamCheckFlg3 _at_ DSG_PARA_MAP_ADDR+20;
129
130 //Ԥ<><D4A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x04
131 //Reserved
132
133 //<2F>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x05 langth=5
134 U16 xdata E2uiDSG1PWMFreq _at_ DSG_PWM_PARA_MAP_ADDR;
135 U8 xdata E2ucDSG1PWMRatioL _at_ DSG_PWM_PARA_MAP_ADDR+2;
136 U8 xdata E2ucDSG1PWMRatioH _at_ DSG_PWM_PARA_MAP_ADDR+3;
137 U8 xdata E2ucRamCheckFlg5 _at_ DSG_PWM_PARA_MAP_ADDR+4;
138
139 //<2F><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x06 langth=11
140 U16 xdata E2uiTempOTC _at_ CHG_TEMP_PARA_MAP_ADDR;
141 U16 xdata E2uiTempOTCR _at_ CHG_TEMP_PARA_MAP_ADDR+2;
142 U16 xdata E2uiTempUTC _at_ CHG_TEMP_PARA_MAP_ADDR+4;
143 U16 xdata E2uiTempUTCR _at_ CHG_TEMP_PARA_MAP_ADDR+6;
144 U8 xdata E2ucTempDelay _at_ CHG_TEMP_PARA_MAP_ADDR+8;
145 U8 xdata E2ucTempRDelay _at_ CHG_TEMP_PARA_MAP_ADDR+9;
146 U8 xdata E2ucRamCheckFlg6 _at_ CHG_TEMP_PARA_MAP_ADDR+10;
147
148 //<2F>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x07 langth=9
149 U16 xdata E2uiTempOTD _at_ DSG_TEMP_PARA_MAP_ADDR;
150 U16 xdata E2uiTempOTDR _at_ DSG_TEMP_PARA_MAP_ADDR+2;
151 U16 xdata E2uiTempUTD _at_ DSG_TEMP_PARA_MAP_ADDR+4;
152 U16 xdata E2uiTempUTDR _at_ DSG_TEMP_PARA_MAP_ADDR+6;
153 U8 xdata E2ucRamCheckFlg7 _at_ DSG_TEMP_PARA_MAP_ADDR+8;
154
155 //ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x08 langth=8
156 U16 xdata E2uiBalanceVol _at_ BAL_PARA_MAP_ADDR;
157 U16 xdata E2uiBalanceVolDiff _at_ BAL_PARA_MAP_ADDR+2;
158 S16 xdata E2siBalCurrent _at_ BAL_PARA_MAP_ADDR+4;
159 U8 xdata E2ucBalanceDelay _at_ BAL_PARA_MAP_ADDR+6;
160 U8 xdata E2ucRamCheckFlg8 _at_ BAL_PARA_MAP_ADDR+7;
161
162 //<2F><><EFBFBD><EFBFBD>ͳ<EFBFBD>Ʋ<EFBFBD><C6B2><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x09 length=17
163 U8 xdata E2ucSOC _at_ SOC_PARA_MAP_ADDR;
164 U32 xdata E2ulDfRC _at_ SOC_PARA_MAP_ADDR+1;
165 S32 xdata E2slDsgEndCurr _at_ SOC_PARA_MAP_ADDR+5; //<2F>ŵ<EFBFBD><C5B5><EFBFBD>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>
166 U32 xdata E2ulCycleThresholdCount _at_ SOC_PARA_MAP_ADDR+9;
167 U16 xdata E2uiLastCCount _at_ SOC_PARA_MAP_ADDR+13;
168 U8 xdata E2ucDsgEndFlg _at_ SOC_PARA_MAP_ADDR+15; //<2F>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־
169 U8 xdata E2ucRamCheckFlg9 _at_ SOC_PARA_MAP_ADDR+16;
170
171
172 //AFE<46><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0A langth=4
173 U8 xdata E2ucAFEProtectConfig _at_ AFE_PARA_MAP_ADDR;
174 U16 xdata E2uiAFEOVvol _at_ AFE_PARA_MAP_ADDR+1;
175 U8 xdata E2ucRamCheckFlgA _at_ AFE_PARA_MAP_ADDR+3;
176
修改均衡起始电压为50mv
2025-02-19 06:13:28 +00:00
C51 COMPILER V9.01 MEMORY 02/19/2025 10:42:27 PAGE 4
First commit
2025-02-06 07:35:32 +00:00
177 //У׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0B langth=12
178 U16 xdata E2uiVPackGain _at_ CALI_PARA_MAP_ADDR;
179 S16 xdata E2siCadcGain _at_ CALI_PARA_MAP_ADDR+2;
180 S16 xdata E2siCadcOffset _at_ CALI_PARA_MAP_ADDR+4;
181 S16 xdata E2siTS0Offset _at_ CALI_PARA_MAP_ADDR+6;
182 S16 xdata E2siTS1Offset _at_ CALI_PARA_MAP_ADDR+8;
183 U8 xdata E2ucCalibrated _at_ CALI_PARA_MAP_ADDR+10;
184 U8 xdata E2ucRamCheckFlgB _at_ CALI_PARA_MAP_ADDR+11;
185
186 U8 xdata Reserved[RESERVED_DATA_LEN] _at_ RESERVED_DATA_MAP_ADDR;
187
188 //DataflashCheck
189 U16 xdata E2uiCheckFlag _at_ XRAM_MAP_ADDR+510;
190
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = ---- ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = 7 ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)