590 lines
14 KiB
C
590 lines
14 KiB
C
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/********************************************************************************
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Copyright (C), Sinowealth Electronic. Ltd.
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Author: Sino
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Version: V0.0
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Date: 2020/04/26
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History:
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V2.0 2020/04/26 Preliminary
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********************************************************************************/
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#include "Main.h"
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/*************************************************************************************************
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: InitVar
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD>Ƿ<EFBFBD>0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ClrRam()<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD><EFBFBD>ѽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Xdata/Idata/Data<EFBFBD><EFBFBD>ȫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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*************************************************************************************************/
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void InitVar(void)
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{
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ucBalanceStep = BALANCE_ENABLE;
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MemorySet((U8 xdata *)slCadcCurBuf, 0, sizeof(slCadcCurBuf));
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MemorySet((U8 xdata *)Info.uiVCell, 0, sizeof(Info.uiVCell));
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Info.uiTS[0] = 2731;
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Info.uiTS[1] = 2731;
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bSlowDischarge = 0;
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bMidDischarge = 0;
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ucDsgingSpeed = 2;
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bFastDischarge = 1;
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bPorSelfTestFlg = 1;
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ucTempeMiddle = 80;
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}
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/*************************************************************************************************
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: SysParaInit
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>MCU Flash<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ<EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Բ<EFBFBD><EFBFBD>ֱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>г<EFBFBD>ʼ<EFBFBD><EFBFBD>
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*************************************************************************************************/
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void SysParaInit(void)
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{
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if(McuFlashCheckFlg(MCUFLASH_BK1_FLG_ADDR))
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{
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McuFlashRead(MCUFLASH_BK1_ADDR, XRAM_MAP_ADDR, 512);
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if(!McuFlashCheckFlg(MCUFLASH_BK2_FLG_ADDR))
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{
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McuFlashWrite(MCUFLASH_BK2_ADDR, XRAM_MAP_ADDR); //<2F><><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>2
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}
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}
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else if(McuFlashCheckFlg(MCUFLASH_BK2_FLG_ADDR))
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{
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McuFlashRead(MCUFLASH_BK2_ADDR, XRAM_MAP_ADDR, 512);
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McuFlashWrite(MCUFLASH_BK1_ADDR, XRAM_MAP_ADDR); //<2F><><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>1
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}
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else
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{
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bMcuFlashErr = 1;
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return;
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}
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uiPackConfig = E2uiPackConfigMap;
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Info.uiPackConfig = uiPackConfig;
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Info.ulFCC = E2ulFCC;
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Info.uiCycleCount = E2uiCycleCount;
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ucCellNum = (uiPackConfig&0x0007)+3; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ó<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>о<EFBFBD><D0BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Offset
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if(ucCellNum==5 || ucCellNum==10)
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{
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ucCellNumOffset = 0;
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}
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else if(ucCellNum==4 || ucCellNum==9)
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{
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ucCellNumOffset = 1;
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}
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else
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{
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ucCellNumOffset = 2;
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}
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}
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/*************************************************************************************************
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: InitIRQ
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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*************************************************************************************************/
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void InitIRQ(void)
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{
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IrqDis(); //<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD>ж<EFBFBD>Դ
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#if (UART0_DEFINE != 0)
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IrqUart0En(); //<2F><>ʼ<EFBFBD><CABC>UART0<54>ж<EFBFBD>ʹ<EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD>ݾ<EFBFBD><DDBE><EFBFBD>ʹ<EFBFBD><CAB9>UARTģ<54><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1> //<2F><><EFBFBD><EFBFBD>UART0<54>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λָ<CEBB><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#endif
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#if (UART1_DEFINE != 0)
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IrqUart1En(); //<2F><>ʼ<EFBFBD><CABC>UART1<54>ж<EFBFBD>ʹ<EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD>ݾ<EFBFBD><DDBE><EFBFBD>ʹ<EFBFBD><CAB9>UARTģ<54><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>
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#endif
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#if (UART2_DEFINE != 0)
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IrqUart2En(); //<2F><>ʼ<EFBFBD><CABC>UART2<54>ж<EFBFBD>ʹ<EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD>ݾ<EFBFBD><DDBE><EFBFBD>ʹ<EFBFBD><CAB9>UARTģ<54><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>
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#endif
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IrqTimer3FlgClr(); //ʹ<><CAB9>Timer3<72>ж<EFBFBD>
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IrqTimer3En();
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IrqINT4xChEn(INT4_EXS45 | INT4_EXS46);
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IrqINT4Trig(INT4_TRIG_FALLING); //<2F>½<EFBFBD><C2BD>ش<EFBFBD><D8B4><EFBFBD>
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IrqINT4FlgClr(); //<2F><><EFBFBD>ⲿ<EFBFBD>жϱ<D0B6>־
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IrqINT4En(); //ʹ<><CAB9><EFBFBD>ⲿ<EFBFBD>ж<EFBFBD>4
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IrqEn();
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}
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/*************************************************************************************************
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: InitGPIO
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>I/O<EFBFBD>˿ڣ<EFBFBD>δʹ<EFBFBD>õ<EFBFBD>I/O<EFBFBD><EFBFBD>Ĭ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD>ƽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>MCU<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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P0.7[TXD], P0.6[RXD], P0.5[SCL], P0.4[SDA], P0.3[BLPW], P0.2[], P0.1[], P0.0[],
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P0.7ST[1], P0.6ST[1], P0.5ST[1], P0.4ST[1], P0.3ST[1], P0.2ST[0], P0.1ST[0], P0.0ST[0], P0 = 0xF8;
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P0.7CR[1], P0.6CR[0], P0.5CR[0], P0.4CR[0], P0.3CR[1], P0.2CR[1], P0.1CR[1], P0.0CR[1], P0CR = 0x8F;
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P0.7PC[1], P0.6PC[1], P0.5PC[0], P0.4PC[0], P0.3PC[1], P0.2PC[0], P0.1PC[0], P0.0PC[0], P0PCR = 0xC8;
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P1.7[RESET],P1.6[], P1.5[], P1.4[], P1.3[], P1.2[], P1.1[], P1.0[],
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P1.7ST[1], P1.6ST[0], P1.5ST[0], P1.4ST[0], P1.3ST[0], P1.2ST[0], P1.1ST[0], P1.0ST[0], P1 = 0x80;
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P1.7CR[0], P1.6CR[1], P1.5CR[1], P1.4CR[1], P1.3CR[1], P1.2CR[1], P1.1CR[1], P1.0CR[1], P1CR = 0x7F;
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P1.7PC[1], P1.6PC[0], P1.5PC[0], P1.4PC[0], P1.3PC[0], P1.2PC[0], P1.1PC[0], P1.0PC[0], P1PCR = 0x80;
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P2.7[KEY_M],P2.6[ALARM],P2.5[CTLD], P2.4[LED5], P2.3[LED4], P2.2[LED3], P2.1[LED2], P2.0[LED1],
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P2.7ST[1], P2.6ST[1], P2.5ST[1], P2.4ST[0], P2.3ST[0], P2.2ST[0], P2.1ST[0], P2.0ST[0], P2 = 0xE0;
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P2.7CR[0], P2.6CR[0], P2.5CR[1], P2.4CR[1], P2.3CR[1], P2.2CR[1], P2.1CR[1], P2.0CR[1], P2CR = 0x3F;
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P2.7PC[1], P2.6PC[1], P2.5PC[0], P2.4PC[0], P2.3PC[0], P2.2PC[0], P2.1PC[0], P2.0PC[0], P2PCR = 0xC0;
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P3.7[], P3.6[], P3.5[LED6], P3.4[XTAL1],P3.3[XTAL2],P3.2[], P3.1[], P3.0[KLED],
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P3.7ST[0], P3.6ST[0], P3.5ST[0], P3.4ST[1], P3.3ST[1], P3.2ST[0], P3.1ST[0], P3.0ST[1], P3 = 0x19;
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P3.7CR[1], P3.6CR[1], P3.5CR[1], P3.4CR[0], P3.3CR[0], P3.2CR[1], P3.1CR[1], P3.0CR[0], P3CR = 0xE6;
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P3.7PC[0], P3.6PC[0], P3.5PC[0], P3.4PC[1], P3.3PC[1], P3.2PC[0], P3.1PC[0], P3.0PC[1], P3PCR = 0x19;
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*************************************************************************************************/
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/*************************************************************************************************
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: InitGPIO_SL
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
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* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>I/O<EFBFBD>˿ڣ<EFBFBD>δʹ<EFBFBD>õ<EFBFBD>I/O<EFBFBD><EFBFBD>Ĭ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD>ƽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>MCU<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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P0.7[TX], P0.6[RX], P0.5[SCL], P0.4[SDA], P0.3[], P0.2[], P0.1[], P0.0[], IO״̬:P0.[7,6,5,4,3]<EFBFBD><EFBFBD>Ч
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P0.7ST[1], P0.6ST[1], P0.5ST[1], P0.4ST[1], P0.3ST[0], P0.2ST[0], P0.1ST[0], P0.0ST[0], P0 = 0xF0; IO״̬:P0.[7,6,5,4,3]<EFBFBD><EFBFBD>Ч
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P0.7CR[1], P0.6CR[0], P0.5CR[0], P0.4CR[0], P0.3CR[1], P0.2CR[1], P0.1CR[1], P0.0CR[1], P0CR = 0x8F; IO<EFBFBD><EFBFBD><EFBFBD><EFBFBD>:P0.[7,6,5,4,3]<EFBFBD><EFBFBD>Ч,1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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P0.7PC[1], P0.6PC[1], P0.5PC[0], P0.4PC[0], P0.3PC[0], P0.2PC[0], P0.1PC[0], P0.0PC[0], P0PCR = 0xC0; <EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD>ر<EFBFBD>
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P1.7[RESET],P1.6[], P1.5[], P1.4[], P1.3[], P1.2[], P1.1[], P1.0[], IO״̬:P1.[7,6,5,4,3,2]<EFBFBD><EFBFBD>Ч
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P1.7ST[1], P1.6ST[0], P1.5ST[0], P1.4ST[0], P1.3ST[0], P1.2ST[0], P1.1ST[0], P1.0ST[0], P1 = 0x80; IO״̬:P1.[7,6,5,4,3,2]<EFBFBD><EFBFBD>Ч
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P1.7CR[0], P1.6CR[1], P1.5CR[1], P1.4CR[1], P1.3CR[1], P1.2CR[1], P1.1CR[1], P1.0CR[1], P1CR = 0x7F; IO<EFBFBD><EFBFBD><EFBFBD><EFBFBD>:P1.[7,6,5,4,3,2]<EFBFBD><EFBFBD>Ч,1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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P1.7PC[1], P1.6PC[0], P1.5PC[0], P1.4PC[0], P1.3PC[0], P1.2PC[0], P1.1PC[0], P1.0PC[0], P1PCR = 0x80; <EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD>ر<EFBFBD>
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P2.7[], P2.6[ALARM],P2.5[], P2.4[LED], P2.3[], P2.2[], P2.1[], P2.0[485_DE], IO״̬:P2.[7,6,5,4,3,2,1,0]<EFBFBD><EFBFBD>Ч
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P2.7ST[0], P2.6ST[1], P2.5ST[0], P2.4ST[0], P2.3ST[0], P2.2ST[1], P2.1ST[1], P2.0ST[0], P2 = 0x46; IO״̬:P2.[7,6,5,4,3,2,1,0]<EFBFBD><EFBFBD>Ч
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P2.7CR[1], P2.6CR[0], P2.5CR[1], P2.4CR[1], P2.3CR[1], P2.2CR[0], P2.1CR[1], P2.0CR[1], P2CR = 0xBB; IO<EFBFBD><EFBFBD><EFBFBD><EFBFBD>:P2.[7,6,5,4,3,2,1,0]<EFBFBD><EFBFBD>Ч,1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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P2.7PC[0], P2.6PC[1], P2.5PC[0], P2.4PC[0], P2.3PC[0], P2.2PC[1], P2.1PC[1], P2.0PC[1], P2PCR = 0x46; <EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD>ر<EFBFBD>
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P3.7[], P3.6[], P3.5[BAT_V_C], P3.4[XTAL1],P3.3[XTAL2],P3.2[], P3.1[], P3.0[BAT_V], IO״̬:P3.[5,4,3,...,0]<EFBFBD><EFBFBD>Ч
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P3.7ST[0], P3.6ST[0], P3.5ST[0], P3.4ST[1], P3.3ST[1], P3.2ST[0], P3.1ST[0], P3.0ST[0], P3 = 0x18; IO״̬:P3.[5,4,3,...,0]<EFBFBD><EFBFBD>Ч
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P3.7CR[1], P3.6CR[1], P3.5CR[1], P3.4CR[0], P3.3CR[0], P3.2CR[1], P3.1CR[1], P3.0CR[0], P3CR = 0xE6; IO<EFBFBD><EFBFBD><EFBFBD><EFBFBD>:P3.[5,4,3,...,0]<EFBFBD><EFBFBD>Ч,1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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P3.7PC[0], P3.6PC[0], P3.5PC[0], P3.4PC[1], P3.3PC[1], P3.2PC[0], P3.1PC[0], P3.0PC[0], P3PCR = 0x18; <EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD>ر<EFBFBD>
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*************************************************************************************************/
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void InitGPIO(void)
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{
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P0 = 0xF0;
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P0CR = 0x8F;
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P0PCR = 0xC0;
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P1 = 0x80;
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P1CR = 0x7F;
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P1PCR = 0x80;
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P2 = 0x46;
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P2CR = 0xBB;
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P2PCR = 0x46;
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P3 = 0x18;
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P3CR = 0xE6;
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P3PCR = 0x18;
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//UART0<54><30><EFBFBD><EFBFBD>IO<49><4F><EFBFBD><EFBFBD> <20><><EFBFBD>ڹ<EFBFBD><DAB9><EFBFBD>ӳ<EFBFBD><D3B3>ʱע<CAB1><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӦIO<49>ڵļĴ<C4BC><C4B4><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>֤<EFBFBD><D6A4><EFBFBD>ܿ<EFBFBD><DCBF><EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5>
|
|||
|
#if (UART0_DEFINE == 1)
|
|||
|
P0 |= 0xC0;
|
|||
|
P0PCR |= 0x80;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 2)
|
|||
|
P0 |= 0x40;
|
|||
|
P2 |= 0x10;
|
|||
|
P2PCR |= 0x10;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 3)
|
|||
|
P0 |= 0x40;
|
|||
|
P2 |= 0x20;
|
|||
|
P2PCR |= 0x20;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 4)
|
|||
|
P0 |= 0x41;
|
|||
|
P0PCR |= 0x01;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 5)
|
|||
|
P0 |= 0x42;
|
|||
|
P0PCR |= 0x02;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 6)
|
|||
|
P0 |= 0xC0;
|
|||
|
P0PCR |= 0x40;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 7)
|
|||
|
P0 |= 0x80;
|
|||
|
P2 |= 0x10;
|
|||
|
P2PCR |= 0x10;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 8)
|
|||
|
P0 |= 0x80;
|
|||
|
P2 |= 0x20;
|
|||
|
P2PCR |= 0x20;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 9)
|
|||
|
P0 |= 0x81;
|
|||
|
P0PCR |= 0x01;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 10)
|
|||
|
P0 |= 0x82;
|
|||
|
P0PCR |= 0x02;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 11)
|
|||
|
P0 |= 0x40;
|
|||
|
P2 |= 0x10;
|
|||
|
P0PCR |= 0x40;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 12)
|
|||
|
P0 |= 0x80;
|
|||
|
P2 |= 0x10;
|
|||
|
P0PCR |= 0x80;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 13)
|
|||
|
P2 |= 0x30;
|
|||
|
P2PCR |= 0x20;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 14)
|
|||
|
P0 |= 0x01;
|
|||
|
P2 |= 0x10;
|
|||
|
P0PCR |= 0x01;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 15)
|
|||
|
P0 |= 0x02;
|
|||
|
P2 |= 0x10;
|
|||
|
P0PCR |= 0x02;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 16)
|
|||
|
P0 |= 0x40;
|
|||
|
P2 |= 0x20;
|
|||
|
P0PCR |= 0x40;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 17)
|
|||
|
P0 |= 0x80;
|
|||
|
P2 |= 0x20;
|
|||
|
P0PCR |= 0x80;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 18)
|
|||
|
P2 |= 0x30;
|
|||
|
P2PCR |= 0x10;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 19)
|
|||
|
P0 |= 0x01;
|
|||
|
P2 |= 0x20;
|
|||
|
P0PCR |= 0x01;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 20)
|
|||
|
P0 |= 0x02;
|
|||
|
P2 |= 0x20;
|
|||
|
P0PCR |= 0x02;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 21)
|
|||
|
P0 |= 0x81;
|
|||
|
P0PCR |= 0x80;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 22)
|
|||
|
P0 |= 0x01;
|
|||
|
P2 |= 0x10;
|
|||
|
P2PCR |= 0x10;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 23)
|
|||
|
P0 |= 0x01;
|
|||
|
P2 |= 0x20;
|
|||
|
P2PCR |= 0x20;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 24)
|
|||
|
P0 |= 0x41;
|
|||
|
P0PCR |= 0x40;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 25)
|
|||
|
P0 |= 0x03;
|
|||
|
P0PCR |= 0x02;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 26)
|
|||
|
P0 |= 0x82;
|
|||
|
P0PCR |= 0x80;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 27)
|
|||
|
P0 |= 0x02;
|
|||
|
P2 |= 0x10;
|
|||
|
P2PCR |= 0x10;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 28)
|
|||
|
P0 |= 0x02;
|
|||
|
P2 |= 0x20;
|
|||
|
P2PCR |= 0x20;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 29)
|
|||
|
P0 |= 0x42;
|
|||
|
P0PCR |= 0x40;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART0_DEFINE == 30)
|
|||
|
P0 |= 0x03;
|
|||
|
P0PCR |= 0x01;
|
|||
|
#endif
|
|||
|
|
|||
|
//UART1<54><31><EFBFBD><EFBFBD>IO<49><4F><EFBFBD><EFBFBD>
|
|||
|
#if (UART1_DEFINE == 1)
|
|||
|
P1 |= 0x03;
|
|||
|
P1PCR |= 0x02;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 2)
|
|||
|
P1 |= 0x01;
|
|||
|
P3 |= 0x08;
|
|||
|
P3PCR |= 0x08;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 3)
|
|||
|
P1 |= 0x01;
|
|||
|
P3 |= 0x10;
|
|||
|
P3PCR |= 0x10;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 4)
|
|||
|
P1 |= 0x01;
|
|||
|
P2 |= 0x40;
|
|||
|
P2PCR |= 0x40;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 5)
|
|||
|
P1 |= 0x01;
|
|||
|
P2 |= 0x80;
|
|||
|
P2PCR |= 0x80;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 6)
|
|||
|
P1 |= 0x03;
|
|||
|
P1PCR |= 0x01;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 7)
|
|||
|
P1 |= 0x02;
|
|||
|
P3 |= 0x08;
|
|||
|
P3PCR |= 0x08;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 8)
|
|||
|
P1 |= 0x02;
|
|||
|
P3 |= 0x10;
|
|||
|
P3PCR |= 0x10;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 9)
|
|||
|
P1 |= 0x02;
|
|||
|
P2 |= 0x40;
|
|||
|
P2PCR |= 0x40;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 10)
|
|||
|
P1 |= 0x02;
|
|||
|
P2 |= 0x80;
|
|||
|
P2PCR |= 0x80;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 11)
|
|||
|
P1 |= 0x01;
|
|||
|
P3 |= 0x08;
|
|||
|
P1PCR |= 0x01;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 12)
|
|||
|
P1 |= 0x02;
|
|||
|
P3 |= 0x08;
|
|||
|
P1PCR |= 0x01;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 13)
|
|||
|
P3 |= 0x18;
|
|||
|
P3PCR |= 0x10;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 14)
|
|||
|
P3 |= 0x08;
|
|||
|
P2 |= 0x40;
|
|||
|
P2PCR |= 0x40;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 15)
|
|||
|
P3 |= 0x08;
|
|||
|
P2 |= 0x80;
|
|||
|
P2PCR |= 0x80;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 16)
|
|||
|
P1 |= 0x01;
|
|||
|
P3 |= 0x10;
|
|||
|
P1PCR |= 0x01;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 17)
|
|||
|
P1 |= 0x02;
|
|||
|
P3 |= 0x10;
|
|||
|
P1PCR |= 0x02;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 18)
|
|||
|
P3 |= 0x18;
|
|||
|
P3PCR |= 0x08;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 19)
|
|||
|
P3 |= 0x10;
|
|||
|
P2 |= 0x40;
|
|||
|
P2PCR |= 0x40;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 20)
|
|||
|
P3 |= 0x10;
|
|||
|
P2 |= 0x80;
|
|||
|
P2PCR |= 0x80;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 21)
|
|||
|
P1 |= 0x01;
|
|||
|
P2 |= 0x40;
|
|||
|
P1PCR |= 0x01;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 22)
|
|||
|
P1 |= 0x02;
|
|||
|
P2 |= 0x40;
|
|||
|
P1PCR |= 0x02;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 23)
|
|||
|
P2 |= 0x40;
|
|||
|
P3 |= 0x08;
|
|||
|
P3PCR |= 0x08;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 24)
|
|||
|
P3 |= 0x10;
|
|||
|
P2 |= 0x40;
|
|||
|
P3PCR |= 0x10;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 25)
|
|||
|
P2 |= 0xC0;
|
|||
|
P2PCR |= 0x80;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 26)
|
|||
|
P1 |= 0x01;
|
|||
|
P2 |= 0x80;
|
|||
|
P1PCR |= 0x01;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 27)
|
|||
|
P1 |= 0x02;
|
|||
|
P2 |= 0x80;
|
|||
|
P1PCR |= 0x02;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 28)
|
|||
|
P2 |= 0x80;
|
|||
|
P3 |= 0x08;
|
|||
|
P3PCR |= 0x08;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 29)
|
|||
|
P3 |= 0x10;
|
|||
|
P2 |= 0x80;
|
|||
|
P3PCR |= 0x10;
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE == 30)
|
|||
|
P2 |= 0xC0;
|
|||
|
P2PCR |= 0x40;
|
|||
|
#endif
|
|||
|
|
|||
|
//UART2<54><32><EFBFBD><EFBFBD>IO<49><4F><EFBFBD>ã<EFBFBD><C3A3><EFBFBD>ǰdemo<6D><6F><EFBFBD>˴<EFBFBD><CBB4><EFBFBD><EFBFBD><EFBFBD>LED<45><44><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE><EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD>֧<EFBFBD>ִ<EFBFBD><D6B4><EFBFBD>ͨѶ<CDA8><D1B6><EFBFBD><EFBFBD>demo<6D><6F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>ʹ<EFBFBD><CAB9>uart2<74><32><EFBFBD>ڹ<EFBFBD><DAB9><EFBFBD>
|
|||
|
#if (UART2_DEFINE == 1)
|
|||
|
P2 |= 0x06;
|
|||
|
P2PCR |= 0x04;
|
|||
|
#endif
|
|||
|
}
|
|||
|
|
|||
|
/*************************************************************************************************
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: Initial
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>
|
|||
|
*************************************************************************************************/
|
|||
|
void Initial(void)
|
|||
|
{
|
|||
|
McuClockSet(MCU_CLK_24MHz); //<2F><><EFBFBD><EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>24MHz
|
|||
|
|
|||
|
InitGPIO(); //<2F><>ʼ<EFBFBD><CABC>GPIO
|
|||
|
|
|||
|
// ClrRam(); //<2F><><EFBFBD><EFBFBD>MCU RAM<41><4D>XDATA<54><41>IDATA<54><41>DATA<54><41>
|
|||
|
|
|||
|
SysParaInit(); //<2F><>ʼ<EFBFBD><CABC>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>
|
|||
|
|
|||
|
InitVar(); //<2F><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
|||
|
McuTimer3Set(TIM_CLK_128KHz, 5); //<2F><>ʼ<EFBFBD><CABC>Timer<65><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD>128KHz<48><7A><EFBFBD>þ<EFBFBD><C3BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ5mS
|
|||
|
|
|||
|
#if (UART0_DEFINE != 0)
|
|||
|
UART0Init(); //<2F><>ʼ<EFBFBD><CABC>UART0ģ<30>飬9600Bps
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART1_DEFINE != 0)
|
|||
|
UART1Init(); //<2F><>ʼ<EFBFBD><CABC>UART0ģ<30>飬9600Bps
|
|||
|
#endif
|
|||
|
|
|||
|
#if (UART2_DEFINE != 0)
|
|||
|
UART2Init(); //<2F><>ʼ<EFBFBD><CABC>UART0ģ<30>飬9600Bps
|
|||
|
#endif
|
|||
|
|
|||
|
TwiInit(); //<2F><>ʼ<EFBFBD><CABC>TWIģ<49>飬ͨѶƵ<D1B6><C6B5>Ϊ100Khz
|
|||
|
|
|||
|
McuPWM2Set(4000, 100); //<2F><>ʼ<EFBFBD><CABC>PWM2<4D><32>ռ<EFBFBD>ձ<EFBFBD>100%
|
|||
|
|
|||
|
AFEInitReg(); //<2F><>ʼ<EFBFBD><CABC>AFE<46>Ĵ<EFBFBD><C4B4><EFBFBD>
|
|||
|
if(!AFEInit()) //<2F><>ʼ<EFBFBD><CABC>AFE<46><45>MCU<43><55><EFBFBD><EFBFBD>AFE<46><45>V33<33><33><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD>MCU<43><55><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>AFE<46>Ѿ<EFBFBD><EFBFBD><D7BC><EFBFBD><EFBFBD>ͨѶ<CDA8><D1B6>
|
|||
|
{
|
|||
|
bAfeErr = 1;
|
|||
|
}
|
|||
|
AFEClrFlg(); //<2F><><EFBFBD><EFBFBD>AFE״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>
|
|||
|
|
|||
|
if(bEnEEPRomBK)
|
|||
|
{
|
|||
|
if(!E2PRomInit())
|
|||
|
{
|
|||
|
bE2PRErr = 1; //<2F><><EFBFBD><EFBFBD>EEPROMģ<4D><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
}
|
|||
|
|
|||
|
if(!RTCInitTime(&RTC))
|
|||
|
{
|
|||
|
bRTCErr = 1; //<2F><><EFBFBD><EFBFBD>RTCģ<43><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
}
|
|||
|
}
|
|||
|
|
|||
|
InitIRQ(); //<2F><>ʼ<EFBFBD><CABC><EFBFBD>ж<EFBFBD>
|
|||
|
}
|