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ZDBMS/code_app/Memory.c

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First commit
2025-02-06 07:35:32 +00:00
/********************************************************************************
Copyright (C), Sinowealth Electronic. Ltd.
Author: Sino
Version: V0.0
Date: 2020/04/26
History:
V2.0 2020/04/26 Preliminary
********************************************************************************/
#include "Main.h"
//*****************************DATA MEMORY START***************************//
U8 idata STACK[0x100-STACK_ADDR] _at_ STACK_ADDR; //<2F><>ջ
//*****************************BIT MEMORY START***************************//
U16 bdata uiPackConfig;
sbit bCellNum1 = uiPackConfig^8;
sbit bCellNum2 = uiPackConfig^9;
sbit bCellNum3 = uiPackConfig^10;
sbit bLEDNum0 = uiPackConfig^11; //Ԥ<><D4A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9>
sbit bLEDNum1 = uiPackConfig^12;
sbit bTempNum = uiPackConfig^13;
sbit bChgerLock = uiPackConfig^14; //<2F>Ƿ<EFBFBD>֧<EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
sbit bLoadLock = uiPackConfig^15; //<2F>Ƿ<EFBFBD>֧<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
sbit bSC_EN = uiPackConfig^0; //00101011
sbit bOV_EN = uiPackConfig^1;
sbit bOCRC_EN = uiPackConfig^2; //auto reset or nor when OCC
sbit bBAL_EN = uiPackConfig^3;
sbit bPF_EN = uiPackConfig^4; //disable
sbit bCTO_EN = uiPackConfig^5; //cell on
sbit bOCPM = uiPackConfig^6; //disable
sbit bEnEEPRomBK = uiPackConfig^7;
U16 bdata uiPackStatus;
sbit bCHGMOS = uiPackStatus^8;
sbit bDSGMOS = uiPackStatus^9;
sbit bCHGING = uiPackStatus^10;
sbit bDSGING = uiPackStatus^11;
sbit bSlowDischarge = uiPackStatus^12;
sbit bMidDischarge = uiPackStatus^13;
sbit bFastDischarge = uiPackStatus^14;
sbit bFC = uiPackStatus^0;
sbit bFD = uiPackStatus^1;
sbit bVDQ = uiPackStatus^2;
U16 bdata uiBatStatus;
sbit bOV = uiBatStatus^8;
sbit bUV = uiBatStatus^9;
sbit bOCC = uiBatStatus^10;
sbit bOCD1 = uiBatStatus^11;
sbit bOCD2 = uiBatStatus^12;
sbit bOTC = uiBatStatus^0;
sbit bOTD = uiBatStatus^1;
sbit bUTC = uiBatStatus^2;
sbit bUTD = uiBatStatus^3;
sbit bAFE_OV = uiBatStatus^4;
sbit bAFE_SC = uiBatStatus^5;
sbit bCTO = uiBatStatus^6;
U8 bdata ucAFEStatus;
sbit bAfeChger = ucAFEStatus^0;
sbit bAfeLoad = ucAFEStatus^1;
sbit bAfeChging = ucAFEStatus^2;
sbit bAfeDsging = ucAFEStatus^3;
sbit bAfeCHG = ucAFEStatus^4;
sbit bAfeDSG = ucAFEStatus^5;
/**************************************************************************************/
//DataFlash<73><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>
/**************************************************************************************/
//ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʼ SubClassID=0x00 langth=48
U16 xdata E2uiPackConfigMap _at_ SYS_PARA_MAP_ADDR;
U16 xdata E2uiVOC[10] _at_ SYS_PARA_MAP_ADDR+2;
U32 xdata E2ulDesignCapacity _at_ SYS_PARA_MAP_ADDR+22;
U32 xdata E2ulFCC _at_ SYS_PARA_MAP_ADDR+26;
U32 xdata E2ulCycleThreshold _at_ SYS_PARA_MAP_ADDR+30;
U16 xdata E2uiCycleCount _at_ SYS_PARA_MAP_ADDR+34;
U16 xdata E2uiLearnLowTempe _at_ SYS_PARA_MAP_ADDR+36;
U16 xdata E2Reserve _at_ SYS_PARA_MAP_ADDR+38;//<2F><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>Ԥ<EFBFBD><D4A4>ռλ
S16 xdata E2siDfilterCur _at_ SYS_PARA_MAP_ADDR+40;
U8 xdata E2ucLowPowerDeley _at_ SYS_PARA_MAP_ADDR+42;
U8 xdata E2ucChgBKDelay _at_ SYS_PARA_MAP_ADDR+43;
S16 xdata E2siChgBKCur _at_ SYS_PARA_MAP_ADDR+44;
U8 xdata E2ucRTCBKDelay _at_ SYS_PARA_MAP_ADDR+46;
U8 xdata E2ucRamCheckFlg0 _at_ SYS_PARA_MAP_ADDR+47; //ucRamCheckFlg + SubClassID
//<2F>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x01 langth=50
U16 xdata E2uiSWVersion _at_ SYSINFO_MAP_ADDR;
U16 xdata E2uiHWVersion _at_ SYSINFO_MAP_ADDR+2;
U8 xdata E2ucID _at_ SYSINFO_MAP_ADDR+4;
U8 xdata E2ucMNFName[12] _at_ SYSINFO_MAP_ADDR+5;
U32 xdata E2ulMNFDate _at_ SYSINFO_MAP_ADDR+17;
U16 xdata E2uiSerialNum _at_ SYSINFO_MAP_ADDR+21;
U8 xdata E2ucDeviceName[12] _at_ SYSINFO_MAP_ADDR+23;
U8 xdata E2ucDeviceChem[12] _at_ SYSINFO_MAP_ADDR+35;
U16 xdata E2uiChemID _at_ SYSINFO_MAP_ADDR+47;
U8 xdata E2ucRamCheckFlg1 _at_ SYSINFO_MAP_ADDR+49;
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x02 langth=18
U16 xdata E2uiOVvol _at_ CHG_PARA_MAP_ADDR;
U16 xdata E2uiOVRvol _at_ CHG_PARA_MAP_ADDR+2;
U8 xdata E2ucOVDelay _at_ CHG_PARA_MAP_ADDR+4;
U8 xdata E2ucOVRDelay _at_ CHG_PARA_MAP_ADDR+5;
U16 xdata E2uiChgEndVol _at_ CHG_PARA_MAP_ADDR+6;
S16 xdata E2siChgEndCurr _at_ CHG_PARA_MAP_ADDR+8;
U8 xdata E2ucChgEndDelay _at_ CHG_PARA_MAP_ADDR+10;
S32 xdata E2slOCCCurrent _at_ CHG_PARA_MAP_ADDR+11;
U8 xdata E2ucOCCDelay _at_ CHG_PARA_MAP_ADDR+15;
U8 xdata E2ucOCCRDelay _at_ CHG_PARA_MAP_ADDR+16;
U8 xdata E2ucRamCheckFlg2 _at_ CHG_PARA_MAP_ADDR+17;
//<2F>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x03 langth=21
U16 xdata E2uiUVvol _at_ DSG_PARA_MAP_ADDR;
U16 xdata E2uiUVRvol _at_ DSG_PARA_MAP_ADDR+2;
U8 xdata E2ucUVDelay _at_ DSG_PARA_MAP_ADDR+4; //all the delay unit is 500mS
U8 xdata E2ucUVRDelay _at_ DSG_PARA_MAP_ADDR+5;
U16 xdata E2uiDsgEndVol _at_ DSG_PARA_MAP_ADDR+6;
U8 xdata E2ucDsgEndDelay _at_ DSG_PARA_MAP_ADDR+8;
S32 xdata E2slOCD1Current _at_ DSG_PARA_MAP_ADDR+9;
U8 xdata E2ucOCD1Delay _at_ DSG_PARA_MAP_ADDR+13;
S32 xdata E2slOCD2Current _at_ DSG_PARA_MAP_ADDR+14;
U8 xdata E2ucOCD2Delay _at_ DSG_PARA_MAP_ADDR+18;
U8 xdata E2ucLoadRDelay _at_ DSG_PARA_MAP_ADDR+19;
U8 xdata E2ucRamCheckFlg3 _at_ DSG_PARA_MAP_ADDR+20;
//Ԥ<><D4A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x04
//Reserved
//<2F>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x05 langth=5
U16 xdata E2uiDSG1PWMFreq _at_ DSG_PWM_PARA_MAP_ADDR;
U8 xdata E2ucDSG1PWMRatioL _at_ DSG_PWM_PARA_MAP_ADDR+2;
U8 xdata E2ucDSG1PWMRatioH _at_ DSG_PWM_PARA_MAP_ADDR+3;
U8 xdata E2ucRamCheckFlg5 _at_ DSG_PWM_PARA_MAP_ADDR+4;
//<2F><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x06 langth=11
U16 xdata E2uiTempOTC _at_ CHG_TEMP_PARA_MAP_ADDR;
U16 xdata E2uiTempOTCR _at_ CHG_TEMP_PARA_MAP_ADDR+2;
U16 xdata E2uiTempUTC _at_ CHG_TEMP_PARA_MAP_ADDR+4;
U16 xdata E2uiTempUTCR _at_ CHG_TEMP_PARA_MAP_ADDR+6;
U8 xdata E2ucTempDelay _at_ CHG_TEMP_PARA_MAP_ADDR+8;
U8 xdata E2ucTempRDelay _at_ CHG_TEMP_PARA_MAP_ADDR+9;
U8 xdata E2ucRamCheckFlg6 _at_ CHG_TEMP_PARA_MAP_ADDR+10;
//<2F>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x07 langth=9
U16 xdata E2uiTempOTD _at_ DSG_TEMP_PARA_MAP_ADDR;
U16 xdata E2uiTempOTDR _at_ DSG_TEMP_PARA_MAP_ADDR+2;
U16 xdata E2uiTempUTD _at_ DSG_TEMP_PARA_MAP_ADDR+4;
U16 xdata E2uiTempUTDR _at_ DSG_TEMP_PARA_MAP_ADDR+6;
U8 xdata E2ucRamCheckFlg7 _at_ DSG_TEMP_PARA_MAP_ADDR+8;
//ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x08 langth=8
U16 xdata E2uiBalanceVol _at_ BAL_PARA_MAP_ADDR;
U16 xdata E2uiBalanceVolDiff _at_ BAL_PARA_MAP_ADDR+2;
S16 xdata E2siBalCurrent _at_ BAL_PARA_MAP_ADDR+4;
U8 xdata E2ucBalanceDelay _at_ BAL_PARA_MAP_ADDR+6;
U8 xdata E2ucRamCheckFlg8 _at_ BAL_PARA_MAP_ADDR+7;
//<2F><><EFBFBD><EFBFBD>ͳ<EFBFBD>Ʋ<EFBFBD><C6B2><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x09 length=17
U8 xdata E2ucSOC _at_ SOC_PARA_MAP_ADDR;
U32 xdata E2ulDfRC _at_ SOC_PARA_MAP_ADDR+1;
S32 xdata E2slDsgEndCurr _at_ SOC_PARA_MAP_ADDR+5; //<2F>ŵ<EFBFBD><C5B5><EFBFBD>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>
U32 xdata E2ulCycleThresholdCount _at_ SOC_PARA_MAP_ADDR+9;
U16 xdata E2uiLastCCount _at_ SOC_PARA_MAP_ADDR+13;
U8 xdata E2ucDsgEndFlg _at_ SOC_PARA_MAP_ADDR+15; //<2F>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־
U8 xdata E2ucRamCheckFlg9 _at_ SOC_PARA_MAP_ADDR+16;
//AFE<46><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0A langth=4
U8 xdata E2ucAFEProtectConfig _at_ AFE_PARA_MAP_ADDR;
U16 xdata E2uiAFEOVvol _at_ AFE_PARA_MAP_ADDR+1;
U8 xdata E2ucRamCheckFlgA _at_ AFE_PARA_MAP_ADDR+3;
//У׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0B langth=12
U16 xdata E2uiVPackGain _at_ CALI_PARA_MAP_ADDR;
S16 xdata E2siCadcGain _at_ CALI_PARA_MAP_ADDR+2;
S16 xdata E2siCadcOffset _at_ CALI_PARA_MAP_ADDR+4;
S16 xdata E2siTS0Offset _at_ CALI_PARA_MAP_ADDR+6;
S16 xdata E2siTS1Offset _at_ CALI_PARA_MAP_ADDR+8;
U8 xdata E2ucCalibrated _at_ CALI_PARA_MAP_ADDR+10;
U8 xdata E2ucRamCheckFlgB _at_ CALI_PARA_MAP_ADDR+11;
U8 xdata Reserved[RESERVED_DATA_LEN] _at_ RESERVED_DATA_MAP_ADDR;
//DataflashCheck
U16 xdata E2uiCheckFlag _at_ XRAM_MAP_ADDR+510;