140 lines
3.7 KiB
C
140 lines
3.7 KiB
C
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#ifndef __UART_APP_H
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#define __UART_APP_H
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#define UART_SLAVE_ADDR 0x00
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#define UART_CMD_NO 0x01
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#define UART_LENGTH 0x02
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#define UART_DATA 0x03
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#define CMD_RD_EEPROM 0x78
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//<2F><><EFBFBD><EFBFBD>Ϣɨ<CFA2><C9A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#define CELL1 0X01
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#define CELL2 0X02
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#define CELL3 0X03
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#define CELL4 0X04
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#define CELL5 0X05
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#define CELL6 0X06
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#define CELL7 0X07
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#define CELL8 0X08
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#define CELL9 0X09
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#define CELL10 0X0A
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#define TOTAL_VOLTAGE 0X0B
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#define EXT_TEMP1 0X0C
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#define EXT_TEMP2 0X0D
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#define DIE_TEMP1 0X0E
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#define DIE_TEMP2 0X0F
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#define CADC_CURRENT 0X10
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#define FULL_CHG_CAP 0X11
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#define REMAIN_CAP 0X12
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#define R_SOC 0X13
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#define CYCLE_COUNT 0X14
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#define PACK_STATUS 0X15
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#define BATTERY_STATUS 0X16
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#define PACK_CONFIG 0X17
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#define MANUFACTURE_COMMAND 0X18
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//MCU<43><55><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#define DATA_FLASH_COMMAND 0x77
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#define SUB_PAGE1 0x78
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#define SUB_PAGE2 0x79
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#define SUB_PAGE3 0x7A
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#define SUB_PAGE4 0x7B
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#define SUB_PAGE5 0x7C
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#define SUB_PAGE6 0x7D
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#define SUB_PAGE7 0x7E
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#define SUB_PAGE8 0x7F
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#define RTC_SUBID 0x0C
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//У<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#define CALI_VOL_COMMAND 0xA0
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#define CALI_TS1_COMMAND 0xA1
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#define CALI_TS2_COMMAND 0xA2
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#define CALI_CUR_COMMAND 0xA3
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#define CALI_ZERO_CUR_COMMAND 0xA4
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#define CALI_RTC_COMMAND 0xAF
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#define CMD_E2PROM_ERASE 0xB0
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#define CMD_E2PROM_ERASE_4K 0xB1
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#define CMD_VALID_ACK 0x5A
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#define CMD_INVALID_ACK 0xFF
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#define Uart0SendAck() Uart0TxEn(CMD_VALID_ACK)
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#define Uart0SendNack() Uart0TxEn(CMD_INVALID_ACK)
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#define Uart0SendData() Uart0TxEn(ucUart0Buf[ucUart0BufPT])
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#define Uart1SendAck() Uart1TxEn(CMD_VALID_ACK)
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#define Uart1SendNack() Uart1TxEn(CMD_INVALID_ACK)
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#define Uart1SendData() Uart1TxEn(ucUart1Buf[ucUart1BufPT])
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#define Uart2SendAck() Uart2TxEn(CMD_VALID_ACK)
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#define Uart2SendNack() Uart2TxEn(CMD_INVALID_ACK)
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#define Uart2SendData() Uart2TxEn(ucUart2Buf[ucUart2BufPT])
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//IAP<41><50><EFBFBD>ض<EFBFBD><D8B6><EFBFBD>
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#define HEARD1 0x00
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#define HEARD2 0x01
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#define LENGTH 0x02
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#define SOURCE 0x03
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#define TARGET 0x04
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#define COMMAND 0x05
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#define INDEXES 0x06
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#define DATA 0x07
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#define IAP_BMSID 0x07 //<2F><><EFBFBD>ع<EFBFBD><D8B9><EFBFBD>ϵͳ1
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#define IAP_PCID 0x3D //<2F><>λ<EFBFBD><CEBB>ϵͳ
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//IAP&ISP Command
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#define IAP_CMD_HANDSHAKE 0x06
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#define IAP_CMD_BEGIN 0x07
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#define IAP_CMD_TRANS 0x08
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#define IAP_CMD_VERIFY 0x09
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#define IAP_CMD_RESET 0x0A
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#define IAPERROR_CHECKSUM 0x80
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#define IAPERROR_ADDR 0x40
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#define IAPERROR_CMD 0x20
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extern BOOL bISPFlg; //ISP<53><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־<EFBFBD><D6BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ISP<53><50><EFBFBD><EFBFBD>
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extern BOOL bUart0ReadFlg;
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extern BOOL bUart0WriteFlg;
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extern BOOL bUart0SndAckFlg; //UART<52>Ѿ<EFBFBD><D1BE><EFBFBD><EFBFBD><EFBFBD>ACK<43><4B><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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extern BOOL bUart1ReadFlg;
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extern BOOL bUart1WriteFlg;
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extern BOOL bUart1SndAckFlg; //UART<52>Ѿ<EFBFBD><D1BE><EFBFBD><EFBFBD><EFBFBD>ACK<43><4B><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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extern BOOL bUart2ReadFlg;
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extern BOOL bUart2WriteFlg;
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extern BOOL bUart2SndAckFlg; //UART<52>Ѿ<EFBFBD><D1BE><EFBFBD><EFBFBD><EFBFBD>ACK<43><4B><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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extern U8 xdata ucSubClassID;
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extern U8 xdata ucUart0Buf[];
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extern U8 xdata ucUart0BufPT;
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extern U8 xdata ucUart0SndLength;
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extern U8 xdata ucUart0TimeoutCnt;
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extern U8 xdata ucUart1Buf[];
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extern U8 xdata ucUart1BufPT;
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extern U8 xdata ucUart1SndLength;
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extern U8 xdata ucUart1TimeoutCnt;
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extern U8 xdata ucUart2Buf[];
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extern U8 xdata ucUart2BufPT;
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extern U8 xdata ucUart2SndLength;
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extern U8 xdata ucUart2TimeoutCnt;
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extern void InterruptUart0AppRx(U8 RxData);
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extern void InterruptUart0AppTx(void);
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extern void Uart0Check(void);
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extern void InterruptUart1AppRx(U8 RxData);
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extern void InterruptUart1AppTx(void);
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extern void Uart1Check(void);
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extern void InterruptUart2AppRx(U8 RxData);
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extern void InterruptUart2AppTx(void);
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extern void Uart2Check(void);
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#endif
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