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First commit
2025-02-06 07:35:32 +00:00
C51 COMPILER V9.01 INITIAL 02/06/2025 15:28:44 PAGE 1
C51 COMPILER V9.01, COMPILATION OF MODULE INITIAL
OBJECT MODULE PLACED IN .\output\Initial.obj
COMPILER INVOKED BY: D:\Tool\Keil\C51\BIN\C51.EXE code_app\Initial.c LARGE OPTIMIZE(7,SIZE) REGFILE(.\output\MCUCore_Loa
-d.ORC) BROWSE INTVECTOR(0X1000) INCDIR(.\header_app;.\header_drv;.\code_gasguage;.\code_classb\iec60730_lib\include;.\co
-de_classb\iec60730_proc\Include;.\code_classb\config) DEBUG OBJECTEXTEND PRINT(.\output\Initial.lst) OBJECT(.\output\Ini
-tial.obj)
line level source
1 /********************************************************************************
2 Copyright (C), Sinowealth Electronic. Ltd.
3 Author: Sino
4 Version: V0.0
5 Date: 2020/04/26
6 History:
7 V2.0 2020/04/26 Preliminary
8 ********************************************************************************/
9 #include "Main.h"
10
11
12 /*************************************************************************************************
13 * <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: InitVar
14 * <20><> <20><>: <20><>
15 * <20><><EFBFBD><EFBFBD>ֵ: <20><>
16 * <20><> <20><>: <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD>Ƿ<EFBFBD>0<EFBFBD><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ClrRam()<29><><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD><D0A3>ѽ<EFBFBD><D1BD><EFBFBD><EFBFBD><EFBFBD>Xdata/Idata/Data<74><61>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
17 *************************************************************************************************/
18 void InitVar(void)
19 {
20 1 ucBalanceStep = BALANCE_ENABLE;
21 1 MemorySet((U8 xdata *)slCadcCurBuf, 0, sizeof(slCadcCurBuf));
22 1 MemorySet((U8 xdata *)Info.uiVCell, 0, sizeof(Info.uiVCell));
23 1 Info.uiTS[0] = 2731;
24 1 Info.uiTS[1] = 2731;
25 1
26 1 bSlowDischarge = 0;
27 1 bMidDischarge = 0;
28 1 ucDsgingSpeed = 2;
29 1 bFastDischarge = 1;
30 1 bPorSelfTestFlg = 1;
31 1
32 1 ucTempeMiddle = 80;
33 1 }
34
35 /*************************************************************************************************
36 * <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: SysParaInit
37 * <20><> <20><>: <20><>
38 * <20><><EFBFBD><EFBFBD>ֵ: <20><>
39 * <20><> <20><>: <20><>MCU Flash<73><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Բ<EFBFBD><D4B2>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>г<EFBFBD>ʼ<EFBFBD><CABC>
40 *************************************************************************************************/
41 void SysParaInit(void)
42 {
43 1 if(McuFlashCheckFlg(MCUFLASH_BK1_FLG_ADDR))
44 1 {
45 2 McuFlashRead(MCUFLASH_BK1_ADDR, XRAM_MAP_ADDR, 512);
46 2 if(!McuFlashCheckFlg(MCUFLASH_BK2_FLG_ADDR))
47 2 {
48 3 McuFlashWrite(MCUFLASH_BK2_ADDR, XRAM_MAP_ADDR); //<2F><><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>2
49 3 }
50 2 }
51 1 else if(McuFlashCheckFlg(MCUFLASH_BK2_FLG_ADDR))
52 1 {
C51 COMPILER V9.01 INITIAL 02/06/2025 15:28:44 PAGE 2
53 2 McuFlashRead(MCUFLASH_BK2_ADDR, XRAM_MAP_ADDR, 512);
54 2 McuFlashWrite(MCUFLASH_BK1_ADDR, XRAM_MAP_ADDR); //<2F><><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>1
55 2 }
56 1 else
57 1 {
58 2 bMcuFlashErr = 1;
59 2 return;
60 2 }
61 1
62 1 uiPackConfig = E2uiPackConfigMap;
63 1 Info.uiPackConfig = uiPackConfig;
64 1 Info.ulFCC = E2ulFCC;
65 1 Info.uiCycleCount = E2uiCycleCount;
66 1
67 1 ucCellNum = (uiPackConfig&0x0007)+3; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ó<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>о<EFBFBD><D0BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Offset
68 1
69 1 if(ucCellNum==5 || ucCellNum==10)
70 1 {
71 2 ucCellNumOffset = 0;
72 2 }
73 1 else if(ucCellNum==4 || ucCellNum==9)
74 1 {
75 2 ucCellNumOffset = 1;
76 2 }
77 1 else
78 1 {
79 2 ucCellNumOffset = 2;
80 2 }
81 1 }
82
83 /*************************************************************************************************
84 * <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: InitIRQ
85 * <20><> <20><>: <20><>
86 * <20><><EFBFBD><EFBFBD>ֵ: <20><>
87 * <20><> <20><>: <20><>ʼ<EFBFBD><CABC><EFBFBD>ж<EFBFBD>
88 *************************************************************************************************/
89 void InitIRQ(void)
90 {
91 1 IrqDis(); //<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD>ж<EFBFBD>Դ
92 1 #if (UART0_DEFINE != 0)
93 1 IrqUart0En(); //<2F><>ʼ<EFBFBD><CABC>UART0<54>ж<EFBFBD>ʹ<EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD>ݾ<EFBFBD><DDBE><EFBFBD>ʹ<EFBFBD><CAB9>UARTģ<54><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1> //<2F><><EFBFBD><EFBFBD>UART
-0<>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λָ<CEBB><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
94 1 #endif
95 1 #if (UART1_DEFINE != 0)
IrqUart1En(); //<2F><>ʼ<EFBFBD><CABC>UART1<54>ж<EFBFBD>ʹ<EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD>ݾ<EFBFBD><DDBE><EFBFBD>ʹ<EFBFBD><CAB9>UARTģ<54><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>
#endif
98 1 #if (UART2_DEFINE != 0)
IrqUart2En(); //<2F><>ʼ<EFBFBD><CABC>UART2<54>ж<EFBFBD>ʹ<EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD>ݾ<EFBFBD><DDBE><EFBFBD>ʹ<EFBFBD><CAB9>UARTģ<54><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>
#endif
101 1
102 1 IrqTimer3FlgClr(); //ʹ<><CAB9>Timer3<72>ж<EFBFBD>
103 1 IrqTimer3En();
104 1
105 1 IrqINT4xChEn(INT4_EXS45 | INT4_EXS46);
106 1 IrqINT4Trig(INT4_TRIG_FALLING); //<2F>½<EFBFBD><C2BD>ش<EFBFBD><D8B4><EFBFBD>
107 1 IrqINT4FlgClr(); //<2F><><EFBFBD>ⲿ<EFBFBD>жϱ<D0B6>־
108 1 IrqINT4En(); //ʹ<><CAB9><EFBFBD>ⲿ<EFBFBD>ж<EFBFBD>4
109 1
110 1 IrqEn();
111 1 }
112
113
C51 COMPILER V9.01 INITIAL 02/06/2025 15:28:44 PAGE 3
114 /*************************************************************************************************
115 * <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: InitGPIO
116 * <20><> <20><>: <20><>
117 * <20><><EFBFBD><EFBFBD>ֵ: <20><>
118 * <20><> <20><>: <20><>ʼ<EFBFBD><CABC>I/O<>˿ڣ<CBBF>δʹ<CEB4>õ<EFBFBD>I/O<><4F>Ĭ<EFBFBD><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD>ƽ<EFBFBD><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>MCU<43><55><EFBFBD><EFBFBD>
119 P0.7[TXD], P0.6[RXD], P0.5[SCL], P0.4[SDA], P0.3[BLPW], P0.2[], P0.1[], P0.0[],
120 P0.7ST[1], P0.6ST[1], P0.5ST[1], P0.4ST[1], P0.3ST[1], P0.2ST[0], P0.1ST[0], P0.0ST[0], P0 = 0xF8;
121 P0.7CR[1], P0.6CR[0], P0.5CR[0], P0.4CR[0], P0.3CR[1], P0.2CR[1], P0.1CR[1], P0.0CR[1], P0CR = 0x8
-F;
122 P0.7PC[1], P0.6PC[1], P0.5PC[0], P0.4PC[0], P0.3PC[1], P0.2PC[0], P0.1PC[0], P0.0PC[0], P0PCR = 0x
-C8;
123
124 P1.7[RESET],P1.6[], P1.5[], P1.4[], P1.3[], P1.2[], P1.1[], P1.0[],
125 P1.7ST[1], P1.6ST[0], P1.5ST[0], P1.4ST[0], P1.3ST[0], P1.2ST[0], P1.1ST[0], P1.0ST[0], P1 = 0x80;
126 P1.7CR[0], P1.6CR[1], P1.5CR[1], P1.4CR[1], P1.3CR[1], P1.2CR[1], P1.1CR[1], P1.0CR[1], P1CR = 0x7
-F;
127 P1.7PC[1], P1.6PC[0], P1.5PC[0], P1.4PC[0], P1.3PC[0], P1.2PC[0], P1.1PC[0], P1.0PC[0], P1PCR = 0x
-80;
128
129 P2.7[KEY_M],P2.6[ALARM],P2.5[CTLD], P2.4[LED5], P2.3[LED4], P2.2[LED3], P2.1[LED2], P2.0[LED1],
130 P2.7ST[1], P2.6ST[1], P2.5ST[1], P2.4ST[0], P2.3ST[0], P2.2ST[0], P2.1ST[0], P2.0ST[0], P2 = 0xE0;
131 P2.7CR[0], P2.6CR[0], P2.5CR[1], P2.4CR[1], P2.3CR[1], P2.2CR[1], P2.1CR[1], P2.0CR[1], P2CR = 0x3
-F;
132 P2.7PC[1], P2.6PC[1], P2.5PC[0], P2.4PC[0], P2.3PC[0], P2.2PC[0], P2.1PC[0], P2.0PC[0], P2PCR = 0x
-C0;
133
134 P3.7[], P3.6[], P3.5[LED6], P3.4[XTAL1],P3.3[XTAL2],P3.2[], P3.1[], P3.0[KLED],
135 P3.7ST[0], P3.6ST[0], P3.5ST[0], P3.4ST[1], P3.3ST[1], P3.2ST[0], P3.1ST[0], P3.0ST[1], P3 = 0x19;
136 P3.7CR[1], P3.6CR[1], P3.5CR[1], P3.4CR[0], P3.3CR[0], P3.2CR[1], P3.1CR[1], P3.0CR[0], P3CR = 0xE
-6;
137 P3.7PC[0], P3.6PC[0], P3.5PC[0], P3.4PC[1], P3.3PC[1], P3.2PC[0], P3.1PC[0], P3.0PC[1], P3PCR = 0x
-19;
138 *************************************************************************************************/
139 /*************************************************************************************************
140 * <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: InitGPIO_SL
141 * <20><> <20><>: <20><>
142 * <20><><EFBFBD><EFBFBD>ֵ: <20><>
143 * <20><> <20><>: <20><>ʼ<EFBFBD><CABC>I/O<>˿ڣ<CBBF>δʹ<CEB4>õ<EFBFBD>I/O<><4F>Ĭ<EFBFBD><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD>ƽ<EFBFBD><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>MCU<43><55><EFBFBD><EFBFBD>
144 P0.7[TX], P0.6[RX], P0.5[SCL], P0.4[SDA], P0.3[], P0.2[], P0.1[], P0.0[], IO״̬:P0.[
-7,6,5,4,3]<5D><>Ч
145 P0.7ST[1], P0.6ST[1], P0.5ST[1], P0.4ST[1], P0.3ST[0], P0.2ST[0], P0.1ST[0], P0.0ST[0], P0 = 0xF0;
- IO״̬:P0.[7,6,5,4,3]<5D><>Ч
146 P0.7CR[1], P0.6CR[0], P0.5CR[0], P0.4CR[0], P0.3CR[1], P0.2CR[1], P0.1CR[1], P0.0CR[1], P0CR = 0x8
-F; IO<49><4F><EFBFBD><EFBFBD>:P0.[7,6,5,4,3]<5D><>Ч,1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><30><EFBFBD><EFBFBD>
147 P0.7PC[1], P0.6PC[1], P0.5PC[0], P0.4PC[0], P0.3PC[0], P0.2PC[0], P0.1PC[0], P0.0PC[0], P0PCR = 0x
-C0; <20>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>:1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD>ر<EFBFBD>
148
149 P1.7[RESET],P1.6[], P1.5[], P1.4[], P1.3[], P1.2[], P1.1[], P1.0[], IO״̬:P1.[7,6,5,4
-,3,2]<5D><>Ч
150 P1.7ST[1], P1.6ST[0], P1.5ST[0], P1.4ST[0], P1.3ST[0], P1.2ST[0], P1.1ST[0], P1.0ST[0], P1 = 0x80;
- IO״̬:P1.[7,6,5,4,3,2]<5D><>Ч
151 P1.7CR[0], P1.6CR[1], P1.5CR[1], P1.4CR[1], P1.3CR[1], P1.2CR[1], P1.1CR[1], P1.0CR[1], P1CR = 0x7
-F; IO<49><4F><EFBFBD><EFBFBD>:P1.[7,6,5,4,3,2]<5D><>Ч,1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><30><EFBFBD><EFBFBD>
152 P1.7PC[1], P1.6PC[0], P1.5PC[0], P1.4PC[0], P1.3PC[0], P1.2PC[0], P1.1PC[0], P1.0PC[0], P1PCR = 0x
-80; <20>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>:1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD>ر<EFBFBD>
153
154 P2.7[], P2.6[ALARM],P2.5[], P2.4[LED], P2.3[], P2.2[], P2.1[], P2.0[485_DE], IO״̬:P2.[7,6,5,
-4,3,2,1,0]<5D><>Ч
155 P2.7ST[0], P2.6ST[1], P2.5ST[0], P2.4ST[0], P2.3ST[0], P2.2ST[1], P2.1ST[1], P2.0ST[0], P2 = 0x46;
- IO״̬:P2.[7,6,5,4,3,2,1,0]<5D><>Ч
156 P2.7CR[1], P2.6CR[0], P2.5CR[1], P2.4CR[1], P2.3CR[1], P2.2CR[0], P2.1CR[1], P2.0CR[1], P2CR = 0xB
-B; IO<49><4F><EFBFBD><EFBFBD>:P2.[7,6,5,4,3,2,1,0]<5D><>Ч,1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><30><EFBFBD><EFBFBD>
C51 COMPILER V9.01 INITIAL 02/06/2025 15:28:44 PAGE 4
157 P2.7PC[0], P2.6PC[1], P2.5PC[0], P2.4PC[0], P2.3PC[0], P2.2PC[1], P2.1PC[1], P2.0PC[1], P2PCR = 0x
-46; <20>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>:1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD>ر<EFBFBD>
158
159 P3.7[], P3.6[], P3.5[BAT_V_C], P3.4[XTAL1],P3.3[XTAL2],P3.2[], P3.1[], P3.0[BAT_V], I
-O״̬:P3.[5,4,3,...,0]<5D><>Ч
160 P3.7ST[0], P3.6ST[0], P3.5ST[0], P3.4ST[1], P3.3ST[1], P3.2ST[0], P3.1ST[0], P3.0ST[0], P3 = 0
-x18; IO״̬:P3.[5,4,3,...,0]<5D><>Ч
161 P3.7CR[1], P3.6CR[1], P3.5CR[1], P3.4CR[0], P3.3CR[0], P3.2CR[1], P3.1CR[1], P3.0CR[0], P3CR =
- 0xE6; IO<49><4F><EFBFBD><EFBFBD>:P3.[5,4,3,...,0]<5D><>Ч,1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD><30><EFBFBD><EFBFBD>
162 P3.7PC[0], P3.6PC[0], P3.5PC[0], P3.4PC[1], P3.3PC[1], P3.2PC[0], P3.1PC[0], P3.0PC[0], P3PCR = 0
-x18; <20>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>:1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0<EFBFBD>ر<EFBFBD>
163 *************************************************************************************************/
164 void InitGPIO(void)
165 {
166 1
167 1 P0 = 0xF0;
168 1 P0CR = 0x8F;
169 1 P0PCR = 0xC0;
170 1
171 1 P1 = 0x80;
172 1 P1CR = 0x7F;
173 1 P1PCR = 0x80;
174 1
175 1 P2 = 0x46;
176 1 P2CR = 0xBB;
177 1 P2PCR = 0x46;
178 1
179 1 P3 = 0x18;
180 1 P3CR = 0xE6;
181 1 P3PCR = 0x18;
182 1
183 1 //UART0<54><30><EFBFBD><EFBFBD>IO<49><4F><EFBFBD><EFBFBD> <20><><EFBFBD>ڹ<EFBFBD><DAB9><EFBFBD>ӳ<EFBFBD><D3B3>ʱע<CAB1><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӦIO<49>ڵļĴ<C4BC><C4B4><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>֤<EFBFBD><D6A4><EFBFBD>ܿ<EFBFBD><DCBF><EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5>
184 1 #if (UART0_DEFINE == 1)
185 1 P0 |= 0xC0;
186 1 P0PCR |= 0x80;
187 1 #endif
188 1
189 1 #if (UART0_DEFINE == 2)
P0 |= 0x40;
P2 |= 0x10;
P2PCR |= 0x10;
#endif
194 1
195 1 #if (UART0_DEFINE == 3)
P0 |= 0x40;
P2 |= 0x20;
P2PCR |= 0x20;
#endif
200 1
201 1 #if (UART0_DEFINE == 4)
P0 |= 0x41;
P0PCR |= 0x01;
#endif
205 1
206 1 #if (UART0_DEFINE == 5)
P0 |= 0x42;
P0PCR |= 0x02;
#endif
210 1
211 1 #if (UART0_DEFINE == 6)
P0 |= 0xC0;
P0PCR |= 0x40;
C51 COMPILER V9.01 INITIAL 02/06/2025 15:28:44 PAGE 5
#endif
215 1
216 1 #if (UART0_DEFINE == 7)
P0 |= 0x80;
P2 |= 0x10;
P2PCR |= 0x10;
#endif
221 1
222 1 #if (UART0_DEFINE == 8)
P0 |= 0x80;
P2 |= 0x20;
P2PCR |= 0x20;
#endif
227 1
228 1 #if (UART0_DEFINE == 9)
P0 |= 0x81;
P0PCR |= 0x01;
#endif
232 1
233 1 #if (UART0_DEFINE == 10)
P0 |= 0x82;
P0PCR |= 0x02;
#endif
237 1
238 1 #if (UART0_DEFINE == 11)
P0 |= 0x40;
P2 |= 0x10;
P0PCR |= 0x40;
#endif
243 1
244 1 #if (UART0_DEFINE == 12)
P0 |= 0x80;
P2 |= 0x10;
P0PCR |= 0x80;
#endif
249 1
250 1 #if (UART0_DEFINE == 13)
P2 |= 0x30;
P2PCR |= 0x20;
#endif
254 1
255 1 #if (UART0_DEFINE == 14)
P0 |= 0x01;
P2 |= 0x10;
P0PCR |= 0x01;
#endif
260 1
261 1 #if (UART0_DEFINE == 15)
P0 |= 0x02;
P2 |= 0x10;
P0PCR |= 0x02;
#endif
266 1
267 1 #if (UART0_DEFINE == 16)
P0 |= 0x40;
P2 |= 0x20;
P0PCR |= 0x40;
#endif
272 1
273 1 #if (UART0_DEFINE == 17)
P0 |= 0x80;
P2 |= 0x20;
C51 COMPILER V9.01 INITIAL 02/06/2025 15:28:44 PAGE 6
P0PCR |= 0x80;
#endif
278 1
279 1 #if (UART0_DEFINE == 18)
P2 |= 0x30;
P2PCR |= 0x10;
#endif
283 1
284 1 #if (UART0_DEFINE == 19)
P0 |= 0x01;
P2 |= 0x20;
P0PCR |= 0x01;
#endif
289 1
290 1 #if (UART0_DEFINE == 20)
P0 |= 0x02;
P2 |= 0x20;
P0PCR |= 0x02;
#endif
295 1
296 1 #if (UART0_DEFINE == 21)
P0 |= 0x81;
P0PCR |= 0x80;
#endif
300 1
301 1 #if (UART0_DEFINE == 22)
P0 |= 0x01;
P2 |= 0x10;
P2PCR |= 0x10;
#endif
306 1
307 1 #if (UART0_DEFINE == 23)
P0 |= 0x01;
P2 |= 0x20;
P2PCR |= 0x20;
#endif
312 1
313 1 #if (UART0_DEFINE == 24)
P0 |= 0x41;
P0PCR |= 0x40;
#endif
317 1
318 1 #if (UART0_DEFINE == 25)
P0 |= 0x03;
P0PCR |= 0x02;
#endif
322 1
323 1 #if (UART0_DEFINE == 26)
P0 |= 0x82;
P0PCR |= 0x80;
#endif
327 1
328 1 #if (UART0_DEFINE == 27)
P0 |= 0x02;
P2 |= 0x10;
P2PCR |= 0x10;
#endif
333 1
334 1 #if (UART0_DEFINE == 28)
P0 |= 0x02;
P2 |= 0x20;
P2PCR |= 0x20;
C51 COMPILER V9.01 INITIAL 02/06/2025 15:28:44 PAGE 7
#endif
339 1
340 1 #if (UART0_DEFINE == 29)
P0 |= 0x42;
P0PCR |= 0x40;
#endif
344 1
345 1 #if (UART0_DEFINE == 30)
P0 |= 0x03;
P0PCR |= 0x01;
#endif
349 1
350 1 //UART1<54><31><EFBFBD><EFBFBD>IO<49><4F><EFBFBD><EFBFBD>
351 1 #if (UART1_DEFINE == 1)
P1 |= 0x03;
P1PCR |= 0x02;
#endif
355 1
356 1 #if (UART1_DEFINE == 2)
P1 |= 0x01;
P3 |= 0x08;
P3PCR |= 0x08;
#endif
361 1
362 1 #if (UART1_DEFINE == 3)
P1 |= 0x01;
P3 |= 0x10;
P3PCR |= 0x10;
#endif
367 1
368 1 #if (UART1_DEFINE == 4)
P1 |= 0x01;
P2 |= 0x40;
P2PCR |= 0x40;
#endif
373 1
374 1 #if (UART1_DEFINE == 5)
P1 |= 0x01;
P2 |= 0x80;
P2PCR |= 0x80;
#endif
379 1
380 1 #if (UART1_DEFINE == 6)
P1 |= 0x03;
P1PCR |= 0x01;
#endif
384 1
385 1 #if (UART1_DEFINE == 7)
P1 |= 0x02;
P3 |= 0x08;
P3PCR |= 0x08;
#endif
390 1
391 1 #if (UART1_DEFINE == 8)
P1 |= 0x02;
P3 |= 0x10;
P3PCR |= 0x10;
#endif
396 1
397 1 #if (UART1_DEFINE == 9)
P1 |= 0x02;
P2 |= 0x40;
C51 COMPILER V9.01 INITIAL 02/06/2025 15:28:44 PAGE 8
P2PCR |= 0x40;
#endif
402 1
403 1 #if (UART1_DEFINE == 10)
P1 |= 0x02;
P2 |= 0x80;
P2PCR |= 0x80;
#endif
408 1
409 1 #if (UART1_DEFINE == 11)
P1 |= 0x01;
P3 |= 0x08;
P1PCR |= 0x01;
#endif
414 1
415 1 #if (UART1_DEFINE == 12)
P1 |= 0x02;
P3 |= 0x08;
P1PCR |= 0x01;
#endif
420 1
421 1 #if (UART1_DEFINE == 13)
P3 |= 0x18;
P3PCR |= 0x10;
#endif
425 1
426 1 #if (UART1_DEFINE == 14)
P3 |= 0x08;
P2 |= 0x40;
P2PCR |= 0x40;
#endif
431 1
432 1 #if (UART1_DEFINE == 15)
P3 |= 0x08;
P2 |= 0x80;
P2PCR |= 0x80;
#endif
437 1
438 1 #if (UART1_DEFINE == 16)
P1 |= 0x01;
P3 |= 0x10;
P1PCR |= 0x01;
#endif
443 1
444 1 #if (UART1_DEFINE == 17)
P1 |= 0x02;
P3 |= 0x10;
P1PCR |= 0x02;
#endif
449 1
450 1 #if (UART1_DEFINE == 18)
P3 |= 0x18;
P3PCR |= 0x08;
#endif
454 1
455 1 #if (UART1_DEFINE == 19)
P3 |= 0x10;
P2 |= 0x40;
P2PCR |= 0x40;
#endif
460 1
461 1 #if (UART1_DEFINE == 20)
C51 COMPILER V9.01 INITIAL 02/06/2025 15:28:44 PAGE 9
P3 |= 0x10;
P2 |= 0x80;
P2PCR |= 0x80;
#endif
466 1
467 1 #if (UART1_DEFINE == 21)
P1 |= 0x01;
P2 |= 0x40;
P1PCR |= 0x01;
#endif
472 1
473 1 #if (UART1_DEFINE == 22)
P1 |= 0x02;
P2 |= 0x40;
P1PCR |= 0x02;
#endif
478 1
479 1 #if (UART1_DEFINE == 23)
P2 |= 0x40;
P3 |= 0x08;
P3PCR |= 0x08;
#endif
484 1
485 1 #if (UART1_DEFINE == 24)
P3 |= 0x10;
P2 |= 0x40;
P3PCR |= 0x10;
#endif
490 1
491 1 #if (UART1_DEFINE == 25)
P2 |= 0xC0;
P2PCR |= 0x80;
#endif
495 1
496 1 #if (UART1_DEFINE == 26)
P1 |= 0x01;
P2 |= 0x80;
P1PCR |= 0x01;
#endif
501 1
502 1 #if (UART1_DEFINE == 27)
P1 |= 0x02;
P2 |= 0x80;
P1PCR |= 0x02;
#endif
507 1
508 1 #if (UART1_DEFINE == 28)
P2 |= 0x80;
P3 |= 0x08;
P3PCR |= 0x08;
#endif
513 1
514 1 #if (UART1_DEFINE == 29)
P3 |= 0x10;
P2 |= 0x80;
P3PCR |= 0x10;
#endif
519 1
520 1 #if (UART1_DEFINE == 30)
P2 |= 0xC0;
P2PCR |= 0x40;
#endif
C51 COMPILER V9.01 INITIAL 02/06/2025 15:28:44 PAGE 10
524 1
525 1 //UART2<54><32><EFBFBD><EFBFBD>IO<49><4F><EFBFBD>ã<EFBFBD><C3A3><EFBFBD>ǰdemo<6D><6F><EFBFBD>˴<EFBFBD><CBB4><EFBFBD><EFBFBD><EFBFBD>LED<45><44><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE><EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD>֧<EFBFBD>ִ<EFBFBD><D6B4><EFBFBD>ͨѶ<CDA8><D1B6><EFBFBD><EFBFBD>demo<6D><6F><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>ʹ<EFBFBD><CAB9>uart2<74><32><EFBFBD>ڹ<EFBFBD><DAB9><EFBFBD>
526 1 #if (UART2_DEFINE == 1)
P2 |= 0x06;
P2PCR |= 0x04;
#endif
530 1 }
531
532 /*************************************************************************************************
533 * <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: Initial
534 * <20><> <20><>: <20><>
535 * <20><><EFBFBD><EFBFBD>ֵ: <20><>
536 * <20><> <20><>: <20><>ʼ<EFBFBD><CABC>
537 *************************************************************************************************/
538 void Initial(void)
539 {
540 1 McuClockSet(MCU_CLK_24MHz); //<2F><><EFBFBD><EFBFBD>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>24MHz
541 1
542 1 InitGPIO(); //<2F><>ʼ<EFBFBD><CABC>GPIO
543 1
544 1 // ClrRam(); //<2F><><EFBFBD><EFBFBD>MCU RAM<41><4D>XDATA<54><41>IDATA<54><41>DATA<54><41>
545 1
546 1 SysParaInit(); //<2F><>ʼ<EFBFBD><CABC>ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>
547 1
548 1 InitVar(); //<2F><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
549 1
550 1 McuTimer3Set(TIM_CLK_128KHz, 5); //<2F><>ʼ<EFBFBD><CABC>Timer<65><72><EFBFBD><EFBFBD><EFBFBD><EFBFBD>128KHz<48><7A><EFBFBD>þ<EFBFBD><C3BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ5mS
551 1
552 1 #if (UART0_DEFINE != 0)
553 1 UART0Init(); //<2F><>ʼ<EFBFBD><CABC>UART0ģ<30>飬9600Bps
554 1 #endif
555 1
556 1 #if (UART1_DEFINE != 0)
UART1Init(); //<2F><>ʼ<EFBFBD><CABC>UART0ģ<30>飬9600Bps
#endif
559 1
560 1 #if (UART2_DEFINE != 0)
UART2Init(); //<2F><>ʼ<EFBFBD><CABC>UART0ģ<30>飬9600Bps
#endif
563 1
564 1 TwiInit(); //<2F><>ʼ<EFBFBD><CABC>TWIģ<49>飬ͨѶƵ<D1B6><C6B5>Ϊ100Khz
565 1
566 1 McuPWM2Set(4000, 100); //<2F><>ʼ<EFBFBD><CABC>PWM2<4D><32>ռ<EFBFBD>ձ<EFBFBD>100%
567 1
568 1 AFEInitReg(); //<2F><>ʼ<EFBFBD><CABC>AFE<46>Ĵ<EFBFBD><C4B4><EFBFBD>
569 1 if(!AFEInit()) //<2F><>ʼ<EFBFBD><CABC>AFE<46><45>MCU<43><55><EFBFBD><EFBFBD>AFE<46><45>V33<33><33><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD>MCU<43><55><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>AFE<46>Ѿ<EFBFBD>׼<EFBFBD><D7BC><EFBFBD><EFBFBD>ͨѶ<CDA8><D1B6>
570 1 {
571 2 bAfeErr = 1;
572 2 }
573 1 AFEClrFlg(); //<2F><><EFBFBD><EFBFBD>AFE״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>
574 1
575 1 if(bEnEEPRomBK)
576 1 {
577 2 if(!E2PRomInit())
578 2 {
579 3 bE2PRErr = 1; //<2F><><EFBFBD><EFBFBD>EEPROMģ<4D><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
580 3 }
581 2
582 2 if(!RTCInitTime(&RTC))
583 2 {
584 3 bRTCErr = 1; //<2F><><EFBFBD><EFBFBD>RTCģ<43><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
585 3 }
C51 COMPILER V9.01 INITIAL 02/06/2025 15:28:44 PAGE 11
586 2 }
587 1
588 1 InitIRQ(); //<2F><>ʼ<EFBFBD><CABC><EFBFBD>ж<EFBFBD>
589 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 376 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)