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ZDBMS/code_dataflash/DataFlash.c

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First commit
2025-02-06 07:35:32 +00:00
/********************************************************************************
Copyright (C), Sinowealth Electronic. Ltd.
Author: Sino
Version: V0.0
Date: 2014/09/10
History:
V0.0 2014/09/10 Preliminary
********************************************************************************/
//*** <<< use Configuration Wizard in Context Menu >>> ***
#define _RAM_CHECK_DATA 0x5A
#define _FLASH_CHECK_DATA 0x5AA5
// <h> ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2>(SubClassID=0x00 length=48)
// <h> <20><><EFBFBD>ذ<EFBFBD><D8B0><EFBFBD>Ϣ<EFBFBD><CFA2>E2uiPackConfigMap<61><70>
// <q> <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define _EPCM_LOAD_LOCK 0 //BIT15; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD>ܸ<EFBFBD><DCB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>; 1<><31>ʹ<EFBFBD>ܸ<EFBFBD><DCB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <q> <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define _EPCM_CHARGER_LOCK 0 //BIT14; 0<><30><EFBFBD><EFBFBD>֧<EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>; 1<><31>֧<EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <q> <09>¶ȼ<C2B6><C8BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#define _EPCM_TEMP_NUM 0 //BIT13; 0<><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¶ȼ<C2B6><C8BC><EFBFBD><EFBFBD><EFBFBD> 1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¶ȼ<C2B6><C8BC><EFBFBD><EFBFBD><EFBFBD>
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// <o> LED<45><44>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD>
#define _EPCM_LED_NUM 0 //BIT11~12; δ<><CEB4><EFBFBD><EFBFBD>
// <o> <20><>о<EFBFBD><D0BE><EFBFBD><EFBFBD>
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#define _EPCM_CELL_NUM 4 //BIT8~10; <09><>о<EFBFBD><D0BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>6~10<31><30>
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// <q> <09><><EFBFBD><EFBFBD>EEPROM<4F><4D><EFBFBD><EFBFBD>
#define _EPCM_EEPROM_EN 0 //BIT7; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>EE<45><45><EFBFBD>ݹ<EFBFBD><DDB9><EFBFBD>; 1<><31>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>EE<45><45><EFBFBD>ݹ<EFBFBD><DDB9><EFBFBD>
过流保护间隔一定时间自恢复，欠压过压保护还未验证
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// <q> <09>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>MOS<4F><53><EFBFBD><EFBFBD>
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#define _EPCM_OCPM 0 //BIT6; δ<><CEB4><EFBFBD>ã<EFBFBD>0<EFBFBD><30><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>رշŵ<D5B7>mos 1<><31><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>رճ<D8B1><D5B3>ŵ<EFBFBD>mos<6F><73>
// <q> <09><><EFBFBD>߼<EFBFBD><DFBC><EFBFBD>
#define _EPCM_CTO_EN 1 //BIT5; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD>ܶ<EFBFBD><DCB6>߱<EFBFBD><DFB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>; 1<><31>ʹ<EFBFBD>ܶ<EFBFBD><DCB6>߱<EFBFBD><DFB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <q> <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define _EPCM_PF_EN 1 //BIT4; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD>ܶ<EFBFBD><DCB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>; 1<><31>ʹ<EFBFBD>ܶ<EFBFBD><DCB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <q> <09><><EFBFBD><EFBFBD>
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#define _EPCM_BAL_EN 1 //BIT3; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD>ܾ<EFBFBD><DCBE>⹦<EFBFBD>ܣ<EFBFBD> 1<><31>ʹ<EFBFBD>ܾ<EFBFBD><DCBE>⹦<EFBFBD><E2B9A6>
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// <q> <20><><EFBFBD><EFBFBD><EFBFBD>Իָ<D4BB>
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#define _EPCM_OCRC_EN 1 //BIT2; 0:<3A><>ʹ<EFBFBD>ܹ<EFBFBD><DCB9><EFBFBD><EFBFBD>Իָ<D4BB><D6B8><EFBFBD><EFBFBD>ܣ<EFBFBD> 1<><31>ʹ<EFBFBD>ܹ<EFBFBD><DCB9><EFBFBD><EFBFBD>Իָ<D4BB><D6B8><EFBFBD><EFBFBD><EFBFBD>
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// <q> Ӳ<><D3B2><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD>
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#define _EPCM_OV_EN 0 //BIT1; 0:<3A><>ʹ<EFBFBD><CAB9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD>ܣ<EFBFBD> 1<><31>ʹ<EFBFBD><CAB9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD>
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// <q> Ӳ<><D3B2><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD>
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#define _EPCM_SC 0 //BIT0; 0:<3A><>ʹ<EFBFBD><CAB9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD> 1<><31>ʹ<EFBFBD><CAB9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#define _E2_PACKCONFIGMAP (_EPCM_EEPROM_EN<<15)|(_EPCM_OCPM<<14)|(_EPCM_CTO_EN<<13)|(_EPCM_PF_EN<<12)\
|(_EPCM_BAL_EN<<11)|(_EPCM_OCRC_EN<<10)|(_EPCM_OV_EN<<9)\
|(_EPCM_SC<<8)|(_EPCM_LOAD_LOCK<<7)|(_EPCM_CHARGER_LOCK<<6)\
|(_EPCM_TEMP_NUM<<5)|(_EPCM_LED_NUM<<4)|(_EPCM_CELL_NUM-3) //U16 xdata E2uiPackConfigMap
// </h>
// <h>OCV<43><56>ѹ<EFBFBD><D1B9>mV<6D><56>
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// 0%2.620
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// <o>10%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
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#define _E2_VOC10 3150 //U16 xdata VOC10
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// <o>20%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
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#define _E2_VOC20 3200 //U16 xdata VOC10
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// <o>30%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
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#define _E2_VOC30 3245 //U16 xdata VOC10
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// <o>40%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
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#define _E2_VOC40 3290 //U16 xdata VOC10
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// <o>50%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
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#define _E2_VOC50 3335 //U16 xdata VOC10
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// <o>60%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
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#define _E2_VOC60 3380 //U16 xdata VOC10
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// <o>70%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
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#define _E2_VOC70 3425 //U16 xdata VOC10
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// <o>80%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
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#define _E2_VOC80 3470 //U16 xdata VOC10
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// <o>90%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
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#define _E2_VOC90 3515 //U16 xdata VOC10
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// <o>100%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
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#define _E2_VOC100 3560 //U16 xdata VOC10
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// </h>
// <h><3E><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ԥ<EFBFBD><D4A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>mAh<41><68>
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#define _E2_ulDesignCapacity 7200 //U32 xdata E2ulDesignCapacity
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// <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>mAh<41><68>
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#define _E2_ulFCC 6500 //U32 xdata E2ulFCC
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// <o>ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
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#define _E2_ulCycleThreshold 6000 // U32 xdata E2ulCycleThreshold
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// <o>ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define _E2_uiCycleCount 0 // U16 xdata E2uiCycleCount
// <o><3E><><EFBFBD><EFBFBD>ѧϰ<D1A7><EFBFBD>
#define _E2_uiLearnLowTempe 2881 // U16 xdata E2uiLearnLowTempe
#define _E2_Reserve 0 // U16 xdata E2Reserve Ԥ<><D4A4>ռλ
// <o><3E><><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
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#define _E2_siDfilterCur 50 // U16 xdata E2siDfilterCur
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// <o><3E>͹<EFBFBD><CDB9>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD>ʱ
#define _E2_ucLowPowerDeley 20 // U16 xdata E2ucLowPowerDeley
// <o><3E><><EFBFBD>籸<EFBFBD>ݼ<EFBFBD><DDBC><EFBFBD><EFBFBD><EFBFBD>ʱ
#define _E2_ucChgBKDelay 1 // U16 xdata E2ucChgBKDelay
// <o><3E><><EFBFBD>籸<EFBFBD>ݼ<EFBFBD><DDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define _E2_siChgBKCur 100 // U16 xdata E2siChgBKCur
// <o>RTC<54><43><EFBFBD>ݼ<EFBFBD><DDBC><EFBFBD><EFBFBD><EFBFBD>ʱ
#define _E2_ucRTCBKDelay 5 // U16 xdata E2ucRTCBKDelay
#define _E2_ucRamCheckFlg0 _RAM_CHECK_DATA // U16 xdata E2ucRamCheckFlg0
// </h>
// </h>
// <h><3E>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x01 length=50)
// <o><3E><><EFBFBD><EFBFBD><EFBFBD>汾(EXP:0x0106 = V1.06)<0x0000-0xffff>
#define _E2_SWVersion 0x0215 // U16 xdata SWVersion
// <o>Ӳ<><D3B2><EFBFBD>汾(EXP:0x0106 = V1.06)<0x0000-0xffff>
#define _E2_HWVersion 0x0130 // U16 xdata HWVersion
// <o><3E>豸ID<0x00-0xff>
#define _E2_ID 0x00 // U8 xdata ID
// <s.12><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#define _E2_MNFName "Cerlink" // U8 xdata MNFName[12]
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// <o> <09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>exp<78><70>0x20230404=2023.04.04<EFBFBD><EFBFBD><0x00000000-0xffffffff>
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#define _E2_MNFDate 0x20250212 // U32 xdata MNFDate
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// <o><3E><><EFBFBD>к<EFBFBD><0x0000-0xffff>
#define _E2_SerialNum 0x0000 // U16 xdata SerialNum
// <s.12><3E>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
修改Flash默认电池串数
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#define _E2_DeviceName "SH39F003" // U8 xdata DeviceName[12]
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// <s.4><3E><>о<EFBFBD><D0BE><EFBFBD><EFBFBD>
#define _E2_DeviceChem "LION" // U8 xdata DeviceChem[12]
// <o><3E><>о<EFBFBD><D0BE>ѧID<0x0000-0xffff>
#define _E2_ChemID 0x0000 // U16 xdata ChemID
#define _E2_ucRamCheckFlg1 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg2
// </h>
// <h><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x02 length=18)
// <o><3E><>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
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#define _E2_uiOVvol 3600 // U16 xdata E2uiOVvol
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// <o><3E><>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ֵ
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#define _E2_uiOVRvol 3400 // U16 xdata E2uiOVRvol
// <o><3E><>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱS
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#define _E2_ucDelayOV 2 // U8 xdata E2ucDelayOV
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// <o><3E><>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ʱS
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#define _E2_ucDelayOVR 2 // U8 xdata E2ucDelayOVR
// <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><D6B9>ѹ(mV)
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#define _E2_uiChgEndVol 3500 // U16 xdata E2uiChgEndVol
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// <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>(mA)
#define _E2_siChgEndCurr 100 // S16 xdata E2siChgEndCurr
// <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><D6B9>ʱ(S)
#define _E2_ucChgEndDelay 5 // U8 xdata E2ucChgEndDelay
// <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
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#define _E2_slOCCvol 25000 // U32 xdata E2slOCCvol
// <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱS
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#define _E2_ucDelayOCC 2 // U8 xdata E2ucDelayOCC
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// <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ʱS
#define _E2_ucDelayOCCR 60 // U8 xdata E2ucDelayOCCR
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#define _E2_ucRamCheckFlg2 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg2
// </h>
// <h><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x03 length=21)
// <o>Ƿѹ<C7B7><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ
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#define _E2_uiUVvol 2600 // U16 xdata E2uiUVvol
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// <o>Ƿѹ<C7B7><D1B9><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ѹ
#define _E2_uiUVRvol 3000 // U16 xdata E2uiUVRvol
// <o>Ƿѹ<C7B7><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ
#define _E2_ucDelayUV 2 // U8 xdata E2ucDelayUV
// <o>Ƿѹ<C7B7><D1B9><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ʱ
#define _E2_ucDelayUVR 2 // U8 xdata E2ucDelayUVR
// <o><3E>ŵ<EFBFBD><C5B5><EFBFBD>ֹ<EFBFBD><D6B9>ʱ(S)
#define _E2_ucDsgEndDelay 5 // U8 xdata E2ucDsgEndDelay
// <o><3E>ŵ<EFBFBD><C5B5><EFBFBD>ֹ<EFBFBD><D6B9>ѹ(mV)
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#define _E2_uiDsgEndVol 2700 // U16 xdata E2uiDsgEndVol
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// <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
#define _E2_uiOCDvol -20000 //U32 xdata E2uiOCDvol
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// <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱs
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#define _E2_ucDelayOCD 2 //U8 xdata E2ucDelayOCD
// <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
#define _E2_slOCD2vol -40000 // S32 xdata E2slOCD2vol
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// <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ125mS
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#define _E2_ucDelayOCD2 2 //U8 xdata E2ucDelayOCD2
// <o><3E><><EFBFBD><EFBFBD><EFBFBD>Ƴ<EFBFBD><C6B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ
#define _E2_ucDelayLoadR 4 //U8 xdata E2ucDelayLoadR
#define _E2_ucRamCheckFlg3 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg3
// </h>
// <h><3E>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD>(SubClassID=0x05 length=5)
// <o>PWMƵ<4D><C6B5>(Hz)
#define _E2_DSG1PWMFreq 4000 // U16 xdata DSG1PWMFreq
// <o>PWM<57>͵<EFBFBD>ռ<EFBFBD>ձ<EFBFBD>(%)
#define _E2_DSG1PWMRatioL 30 // U8 xdata DSG1PWMRatioL
// <o>PWM<57>ߵ<EFBFBD>ռ<EFBFBD>ձ<EFBFBD>(%)
#define _E2_DSG1PWMRatioH 70 // U8 xdata DSG1PWMRatioH
#define _E2_ucRamCheckFlg5 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg5
// </h>
// <h><3E><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x06 length=11)
// <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>(_E2_TempOTC=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*10+2731)
no message
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#define _E2_TempOTC 3431 // U16 xdata TempOTC
First commit
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// <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>(_E2_TempOTCR=<3D>ͷ<EFBFBD><CDB7><EFBFBD>*10+2731)
no message
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#define _E2_TempOTCR 3331 // U16 xdata TempOTCR
First commit
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// <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>(_E2_TempUTC=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*10+2731)
no message
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#define _E2_TempUTC 2531 // U16 xdata TempUTC
First commit
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// <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>(_E2_TempUTCR=<3D>ͷ<EFBFBD><CDB7><EFBFBD>*10+2731)
no message
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#define _E2_TempUTCR 2631 // U16 xdata TempUTCR
First commit
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// <o><3E>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD>ʱ(s)
#define _E2_DelayOTC 3 // U8 xdata DelayOTC
// <o><3E>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>ʱ(s)
#define _E2_DelayOTCR 3 // U8 xdata DelayOTCR
#define _E2_ucRamCheckFlg6 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg6
// </h>
// <h><3E>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x07 length=9)
// <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>(_E2_TempOTC=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*10+2731)
#define _E2_TempOTD 3431 // U16 xdata TempOTD
// <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>(_E2_TempOTCR=<3D>ͷ<EFBFBD><CDB7><EFBFBD>*10+2731)
no message
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#define _E2_TempOTDR 3331 // U16 xdata TempOTDR
First commit
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// <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>(_E2_TempUTC=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*10+2731)
no message
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#define _E2_TempUTD 2531 // U16 xdata TempUTD
First commit
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// <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>(_E2_TempUTCR=<3D>ͷ<EFBFBD><CDB7><EFBFBD>*10+2731)
no message
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#define _E2_TempUTDR 2631 // U16 xdata TempUTDR
First commit
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#define _E2_ucRamCheckFlg7 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg6
// </h>
// <h>ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x08 length=8)
// <o>ƽ<><C6BD><EFBFBD><EFBFBD>ѹ(mV)
no message
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#define _E2_BalanceVol 3000 // U16 xdata BalanceVol
First commit
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// <o>ƽ<><C6BD>ѹ<EFBFBD><D1B9>(mV)
修改均衡起始电压为50mv
2025-02-19 06:13:28 +00:00
#define _E2_BalanceVolDiff 50 // U16 xdata BalanceVolDiff
First commit
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// <o>ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(mA)
#define _E2_BalCurrent 100 // S16 xdata BalCurrent
// <o>ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ(S)
#define _E2_BalanceDelay 2 // U8 xdata BalanceDelay
#define _E2_ucRamCheckFlg8 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg8
// </h>
// <h><3E><><EFBFBD><EFBFBD>ͳ<EFBFBD>Ʋ<EFBFBD><C6B2><EFBFBD>(SubClassID=0x09 length=17)
// <o><3E><><EFBFBD><EFBFBD><EFBFBD>ٷֱ<D9B7>SOC(%)
#define _E2_ucSOC 100 // U8 xdata E2ucSOC
// <o>ʣ<><CAA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>E2ulDfRC(mAh)
#define _E2_ulDfRC 3000 // U32 xdata E2ulLastFCC
// <o><3E>ŵ<EFBFBD><C5B5><EFBFBD>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>
#define _E2_slDsgEndCurr -5000 // U32 xdata E2slDsgEndCurr
// <o><3E>ŵ<EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
#define _E2_ulCycleThresholdCount 0 // U32 xdata E2ulCycleThresholdCount
// <o><3E>ϴθ<CFB4><CEB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define _E2_uiLastCCount 0 // U16 xdata E2uiLastCCount
// <o><3E>ŵ<EFBFBD><C5B5><EFBFBD>ֹ<EFBFBD><D6B9>־
#define _E2_ucDsgEndFlg 0 //U8 xdata E2ucDsgEndFlg
#define _E2_ucRamCheckFlg9 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg9
// </h>
// <h>AFE<46><45><EFBFBD><EFBFBD>(SubClassID=0x0A length=4)
// <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define _E2_AFEProtectConfig 0x74 // U8 xdata AFEProtectConfig
// <o>Ӳ<><D3B2><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
#define _E2_AFEOVvol 4400 // U16 xdata AFEOVvol
#define _E2_ucRamCheckFlgA _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlgA
// </h>
// <h>У׼<D0A3><D7BC><EFBFBD><EFBFBD>(SubClassID=0x0B length=12)
// <o><3E><>ѹУ׼<D0A3><D7BC><EFBFBD><EFBFBD>
#define _E2_uiVPackGain 2594 // U16 xdata E2uiVPackGain
// <o><3E><><EFBFBD><EFBFBD>У׼<D0A3><D7BC><EFBFBD><EFBFBD>
no message
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#define _E2_siCadcGain -89 // S16 xdata E2siCadcGain
First commit
2025-02-06 07:35:32 +00:00
// <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ư
no message
2025-02-14 08:59:29 +00:00
#define _E2_siCadcOffset 4 // S16 xdata E2siCadcOffset
First commit
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// <o><3E>ⲿ<EFBFBD><EFBFBD><C2B6><EFBFBD>Ư(TS0)
#define _E2_siTS0Offset 0 // S16 xdata E2siTS0Offset
// <o><3E>ⲿ<EFBFBD><EFBFBD><C2B6><EFBFBD>Ư(TS1)
#define _E2_siTS1Offset 0 // S16 xdata E2siTS1Offset
// <o>У׼<D0A3><D7BC><EFBFBD><EFBFBD>Ԥ<EFBFBD><D4A4>
#define _E2_ucCalibrated 0 // U8 xdata E2ucCalibrated
#define _E2_ucRamCheckFlgB _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlgB
// </h>
/*****************************************************************************************************************/
/*****************************************************************************************************************/
/*****************************************************************************************************************/
/*****************************************************************************************************************/
/*****************************************************************************************************************/
/*****************************************************************************************************************/
/*****************************************************************************************************************/
/*****************************************************************************************************************/
/*****************************************************************************************************************/
/*****************************************************************************************************************/
/*****************************************************************************************************************/
/*****************************************************************************************************************/
struct DataFlashStu
{
//ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʼ SubClassID=0x00 length=48
unsigned int E2uiPackConfigMap;
unsigned int E2uiVOC[10];
unsigned long E2ulDesignCapacity;
unsigned long E2ulFCC;
unsigned long E2ulCycleThreshold;
unsigned int E2uiCycleCount;
unsigned int E2uiLearnLowTempe;
unsigned int E2Reserve;
signed int E2siDfilterCur;
unsigned char E2ucLowPowerDeley;
unsigned char E2ucChgBKDelay;
unsigned int E2siChgBKCur;
unsigned char E2ucRTCBKDelay;
unsigned char E2ucRamCheckFlg0;
//<2F>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x01 langth=50
unsigned int E2uiSWVersion;
unsigned int E2uiHWVersion;
unsigned char E2ucID;
unsigned char E2ucMNFName[12];
unsigned long E2ulMNFDate;
unsigned int E2uiSerialNum;
unsigned char E2ucDeviceName[12];
unsigned char E2ucDeviceChem[12];
unsigned int E2uiChemID;
unsigned char E2ucRamCheckFlg1;
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x02 langth=18
unsigned int E2uiOVvol;
unsigned int E2uiOVRvol;
unsigned char E2ucOVDelay;
unsigned char E2ucOVRDelay;
unsigned int E2uiChgEndVol0;
signed int E2siChgEndCurr0;
unsigned char E2ucChgEndDelay0;
signed long E2slOCCvol;
unsigned char E2ucDelayOCC;
unsigned char E2ucDelayOCCR;
unsigned char E2ucRamCheckFlg2;
//<2F>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x03 langth=21
unsigned int E2uiUVvol;
unsigned int E2uiUVRvol;
unsigned char E2ucDelayUV;
unsigned char E2ucDelayUVR;
unsigned int E2uiDsgEndVol;
unsigned char E2ucDsgEndDelay;
signed long E2uiOCDvol;
unsigned char E2ucDelayOCD;
signed long E2slOCD2vol;
unsigned char E2ucDelayOCD2;
unsigned char E2ucDelayLoadR;
unsigned char E2ucRamCheckFlg3;
//<2F>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x05 langth=5
unsigned int DSG1PWMFreq;
unsigned char DSG1PWMRatioL;
unsigned char DSG1PWMRatioH;
unsigned char E2ucRamCheckFlg5;
//<2F><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x06 langth=11
unsigned int TempOTC;
unsigned int TempOTCR;
unsigned int TempUTC;
unsigned int TempUTCR;
unsigned char DelayOTC;
unsigned char DelayOTCR;
unsigned char E2ucRamCheckFlg6;
//<2F>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x07 langth=9
unsigned int TempOTD;
unsigned int TempOTDR;
unsigned int TempUTD;
unsigned int TempUTDR;
unsigned char E2ucRamCheckFlg7;
//ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x08 langth=8
unsigned int BalanceVol;
unsigned int BalanceVolDiff;
unsigned int BalCurrent;
unsigned char BalanceDelay;
unsigned char E2ucRamCheckFlg8;
//<2F><><EFBFBD><EFBFBD>ͳ<EFBFBD><CDB3> SubClassID=0x09 length=17
unsigned char E2ucSOC;
unsigned long E2ulDfRC;
signed long E2slDsgEndCurr;
unsigned long E2ulCycleThresholdCount;
unsigned int E2uiLastCCount;
unsigned char E2ucDsgEndFlg;
unsigned char E2ucRamCheckFlg9;
//AFE<46><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0A length=4
unsigned char AFEProtectConfig;
unsigned int AFEOVvol;
unsigned char E2ucRamCheckFlgA;
//У׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0B length=12
unsigned int E2uiVPackGain;
signed int E2siCadcGain;
unsigned int E2siCadcOffset;
unsigned int E2siTS0Offset;
unsigned int E2siTS1Offset;
unsigned char E2ucCalibrated;
unsigned char E2ucRamCheckFlgB;
};
union DataFlashUn
{
struct DataFlashStu DataFlashStu0; /*һ<><D2BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ṹ<EFBFBD><E1B9B9><EFBFBD>ٶ<EFBFBD><D9B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
unsigned char reversed[510];
};
struct DataFlashStr
{
union DataFlashUn DataFlashUnRaw;
unsigned int FlashCheck1;
union DataFlashUn DataFlashUnBak;
unsigned int FlashCheck2;
};
struct DataFlashStr code dataflashstr =
{
/*****************************************************************************************************************/
//<2F><><EFBFBD><EFBFBD>A<EFBFBD><41>
/*****************************************************************************************************************/
//ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʼ SubClassID=0x00 length=48
{
_E2_PACKCONFIGMAP, //U16 xdata E2uiPackConfigMap
_E2_VOC10, //U16 xdata VOC10
_E2_VOC20, //U16 xdata VOC20
_E2_VOC30, //U16 xdata VOC30
_E2_VOC40, //U16 xdata VOC40
_E2_VOC50, //U16 xdata VOC50
_E2_VOC60, //U16 xdata VOC60
_E2_VOC70, //U16 xdata VOC70
_E2_VOC80, //U16 xdata VOC80
_E2_VOC90, //U16 xdata VOC90
_E2_VOC100, //U16 xdata VOC100
_E2_ulDesignCapacity, // U32 xdata E2ulDesignCapacity
_E2_ulFCC, // U32 xdata E2ulFCC
_E2_ulCycleThreshold, // U32 xdata E2uiCycleThreshold
_E2_uiCycleCount, // U16 xdata E2uiCycleCount
_E2_uiLearnLowTempe, // U16 xdata E2uiLearnLowTempe
_E2_Reserve, // U16 xdata E2Reserve
_E2_siDfilterCur, // S16 xdata E2siDfilterCur
_E2_ucLowPowerDeley, // U8 xdata E2ucLowPowerDeley
_E2_ucChgBKDelay, // U8 xdata E2ucChgBKDelay
_E2_siChgBKCur, // S16 xdata E2siChgBKCur
_E2_ucRTCBKDelay, // U8 xdata E2ucRTCBKDelay
_E2_ucRamCheckFlg0, // U8 xdata E2ucRamCheckFlg0
//<2F>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x01 length=50
_E2_SWVersion, //U16 xdata SWVersion
_E2_HWVersion, //U16 xdata HWVersion
_E2_ID, //U8 xdata ID
_E2_MNFName, //U8 xdata MNFName[12]
_E2_MNFDate, //U32 xdata MNFDate
_E2_SerialNum, //U16 xdata SerialNum
_E2_DeviceName, //U8 xdata DeviceName[12]
_E2_DeviceChem, //U8 xdata DeviceChem[12]
_E2_ChemID, //U16 xdata ChemID
_E2_ucRamCheckFlg1, //U8 xdata E2ucRamCheckFlg1
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x02 length=18
_E2_uiOVvol, //U16 xdata E2uiOVvol
_E2_uiOVRvol, //U16 xdata E2uiOVRvol
_E2_ucDelayOV, //U8 xdata E2ucDelayOV
_E2_ucDelayOVR, //U8 xdata E2ucDelayOVR
_E2_uiChgEndVol,
_E2_siChgEndCurr,
_E2_ucChgEndDelay,
_E2_slOCCvol, //S32 xdata E2slOCCvol
_E2_ucDelayOCC, //U8 xdata E2ucDelayOCC
_E2_ucDelayOCCR, //U8 xdata E2ucDelayOCCR
_E2_ucRamCheckFlg2, //U8 xdata E2ucRamCheckFlg2
//<2F>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x03 langth=21
_E2_uiUVvol, //U16 xdata E2uiUVvol
_E2_uiUVRvol, //U16 xdata E2uiUVRvol
_E2_ucDelayUV, //U8 xdata E2ucDelayUV
_E2_ucDelayUVR, //U8 xdata E2ucDelayUVR
_E2_uiDsgEndVol,
_E2_ucDsgEndDelay,
_E2_uiOCDvol, //S32 xdata E2uiOCDvol
_E2_ucDelayOCD, //U8 xdata E2ucDelayOCD
_E2_slOCD2vol, //S32 xdata E2slOCD2vol
_E2_ucDelayOCD2, //U8 xdata E2ucDelayOCD2
_E2_ucDelayLoadR, //U8 xdata E2ucDelayLoadR
_E2_ucRamCheckFlg3, //U8 xdata E2ucRamCheckFlg3
//<2F>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x05 langth=5
_E2_DSG1PWMFreq, //U16 xdata DSG1PWMFreq
_E2_DSG1PWMRatioL, //U8 xdata DSG1PWMRatioL
_E2_DSG1PWMRatioH, //U8 xdata DSG1PWMRatioH
_E2_ucRamCheckFlg5, //U8 xdata E2ucRamCheckFlg5
//<2F><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x06 langth=11
_E2_TempOTC, //U16 xdata TempOTC
_E2_TempOTCR, //U16 xdata TempOTCR
_E2_TempUTC, //U16 xdata TempUTC
_E2_TempUTCR, //U16 xdata TempUTCR
_E2_DelayOTC, //U8 xdata DelayOTC
_E2_DelayOTCR, //U8 xdata DelayOTCR
_E2_ucRamCheckFlg6, //U8 xdata E2ucRamCheckFlg6
//<2F>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x07 langth=9
_E2_TempOTD, //U16 xdata TempOTD
_E2_TempOTDR, //U16 xdata TempOTDR
_E2_TempUTD, //U16 xdata TempUTD
_E2_TempUTDR, //U16 xdata TempUTDR
_E2_ucRamCheckFlg7, //U8 xdata E2ucRamCheckFlg7
//ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x08 langth=8
_E2_BalanceVol, // U16 xdata BalanceVol
_E2_BalanceVolDiff, // U16 xdata BalanceVolDiff
_E2_BalCurrent, // S16 xdata BalCurrent
_E2_BalanceDelay, // U8 xdata BalanceDelay
_E2_ucRamCheckFlg8, // U8 xdata E2ucRamCheckFlg8
//<2F><><EFBFBD><EFBFBD>ͳ<EFBFBD><CDB3> SubClassID=0x09 langth=17
_E2_ucSOC, //U8 xdata E2ucSOC
_E2_ulDfRC, //U32 xdata E2ulLastFCC
_E2_slDsgEndCurr, //U32 xdata E2slDsgEndCurr
_E2_ulCycleThresholdCount, //U32 xdata E2ulCycleThresholdCount
_E2_uiLastCCount,
_E2_ucDsgEndFlg, //U8 xdata E2ucDsgEndFlg
_E2_ucRamCheckFlg9, //U8 xdata E2ucRamCheckFlg9
//AFE<46><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0A langth=4
_E2_AFEProtectConfig, // U8 xdata AFEProtectConfig
_E2_AFEOVvol, // U16 xdata AFEOVvol
_E2_ucRamCheckFlgA, // U8 xdata E2ucRamCheckFlgA
//У׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0B langth=12
_E2_uiVPackGain, //U16 xdata E2uiVPackGain
_E2_siCadcGain, //S16 xdata E2siCadcGain
_E2_siCadcOffset, //S16 xdata E2siCadcOffset
_E2_siTS0Offset, //S16 xdata E2siTS0Offset
_E2_siTS1Offset, //S16 xdata E2siTS1Offset
_E2_ucCalibrated, //S16 xdata E2ucCalibrated
_E2_ucRamCheckFlgB, //U8 xdata E2ucRamCheckFlgB
},
_FLASH_CHECK_DATA, // U16 xdata FlashCheck
/*****************************************************************************************************************/
//<2F><><EFBFBD><EFBFBD>B<EFBFBD><42>
/*****************************************************************************************************************/
/*****************************************************************************************************************/
//ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʼ SubClassID=0x00 langth=48
{
_E2_PACKCONFIGMAP, //U16 xdata E2uiPackConfigMap
_E2_VOC10, //U16 xdata VOC10
_E2_VOC20, //U16 xdata VOC20
_E2_VOC30, //U16 xdata VOC30
_E2_VOC40, //U16 xdata VOC40
_E2_VOC50, //U16 xdata VOC50
_E2_VOC60, //U16 xdata VOC60
_E2_VOC70, //U16 xdata VOC70
_E2_VOC80, //U16 xdata VOC80
_E2_VOC90, //U16 xdata VOC90
_E2_VOC100, //U16 xdata VOC100
_E2_ulDesignCapacity, // U32 xdata E2ulDesignCapacity
_E2_ulFCC, // U32 xdata E2ulFCC
_E2_ulCycleThreshold, // U32 xdata E2uiCycleThreshold
_E2_uiCycleCount, // U16 xdata E2uiCycleCount
_E2_uiLearnLowTempe, // U16 xdata E2uiLearnLowTempe
_E2_Reserve, // U16 xdata E2Reserve
_E2_siDfilterCur, // S16 xdata E2siDfilterCur
_E2_ucLowPowerDeley, // U8 xdata E2ucLowPowerDeley
_E2_ucChgBKDelay, // U8 xdata E2ucChgBKDelay
_E2_siChgBKCur, // S16 xdata E2siChgBKCur
_E2_ucRTCBKDelay, // U8 xdata E2ucRTCBKDelay
_E2_ucRamCheckFlg0, // U8 xdata E2ucRamCheckFlg0
//<2F>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x01 length=50
_E2_SWVersion, //U16 xdata SWVersion
_E2_HWVersion, //U16 xdata HWVersion
_E2_ID, //U8 xdata ID
_E2_MNFName, //U8 xdata MNFName[12]
_E2_MNFDate, //U32 xdata MNFDate
_E2_SerialNum, //U16 xdata SerialNum
_E2_DeviceName, //U8 xdata DeviceName[12]
_E2_DeviceChem, //U8 xdata DeviceChem[12]
_E2_ChemID, //U16 xdata ChemID
_E2_ucRamCheckFlg1, //U8 xdata E2ucRamCheckFlg1
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x02 length=18
_E2_uiOVvol, //U16 xdata E2uiOVvol
_E2_uiOVRvol, //U16 xdata E2uiOVRvol
_E2_ucDelayOV, //U8 xdata E2ucDelayOV
_E2_ucDelayOVR, //U8 xdata E2ucDelayOVR
_E2_uiChgEndVol,
_E2_siChgEndCurr,
_E2_ucChgEndDelay,
_E2_slOCCvol, //S32 xdata E2slOCCvol
_E2_ucDelayOCC, //U8 xdata E2ucDelayOCC
_E2_ucDelayOCCR, //U8 xdata E2ucDelayOCCR
_E2_ucRamCheckFlg2, //U8 xdata E2ucRamCheckFlg2
//<2F>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x03 langth=21
_E2_uiUVvol, //U16 xdata E2uiUVvol
_E2_uiUVRvol, //U16 xdata E2uiUVRvol
_E2_ucDelayUV, //U8 xdata E2ucDelayUV
_E2_ucDelayUVR, //U8 xdata E2ucDelayUVR
_E2_uiDsgEndVol,
_E2_ucDsgEndDelay,
_E2_uiOCDvol, //S32 xdata E2uiOCDvol
_E2_ucDelayOCD, //U8 xdata E2ucDelayOCD
_E2_slOCD2vol, //S32 xdata E2slOCD2vol
_E2_ucDelayOCD2, //U8 xdata E2ucDelayOCD2
_E2_ucDelayLoadR, //U8 xdata E2ucDelayLoadR
_E2_ucRamCheckFlg3, //U8 xdata E2ucRamCheckFlg3
//<2F>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x05 langth=5
_E2_DSG1PWMFreq, //U16 xdata DSG1PWMFreq
_E2_DSG1PWMRatioL, //U8 xdata DSG1PWMRatioL
_E2_DSG1PWMRatioH, //U8 xdata DSG1PWMRatioH
_E2_ucRamCheckFlg5, //U8 xdata E2ucRamCheckFlg5
//<2F><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x06 langth=11
_E2_TempOTC, //U16 xdata TempOTC
_E2_TempOTCR, //U16 xdata TempOTCR
_E2_TempUTC, //U16 xdata TempUTC
_E2_TempUTCR, //U16 xdata TempUTCR
_E2_DelayOTC, //U8 xdata DelayOTC
_E2_DelayOTCR, //U8 xdata DelayOTCR
_E2_ucRamCheckFlg6, //U8 xdata E2ucRamCheckFlg6
//<2F>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x07 langth=9
_E2_TempOTD, //U16 xdata TempOTD
_E2_TempOTDR, //U16 xdata TempOTDR
_E2_TempUTD, //U16 xdata TempUTD
_E2_TempUTDR, //U16 xdata TempUTDR
_E2_ucRamCheckFlg7, //U8 xdata E2ucRamCheckFlg7
//ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x08 langth=8
_E2_BalanceVol, // U16 xdata BalanceVol
_E2_BalanceVolDiff, // U16 xdata BalanceVolDiff
_E2_BalCurrent, // S16 xdata BalCurrent
_E2_BalanceDelay, // U8 xdata BalanceDelay
_E2_ucRamCheckFlg8, // U8 xdata E2ucRamCheckFlg8
//<2F><><EFBFBD><EFBFBD>ͳ<EFBFBD><CDB3> SubClassID=0x09 langth=17
_E2_ucSOC, //U8 xdata E2ucSOC
_E2_ulDfRC, //U32 xdata E2ulLastFCC
_E2_slDsgEndCurr, //U32 xdata E2slDsgEndCurr
_E2_ulCycleThresholdCount, //U32 xdata E2ulCycleThresholdCount
_E2_uiLastCCount,
_E2_ucDsgEndFlg, //U8 xdata E2ucDsgEndFlg
_E2_ucRamCheckFlg9, //U8 xdata E2ucRamCheckFlg9
//AFE<46><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0A langth=4
_E2_AFEProtectConfig, // U8 xdata AFEProtectConfig
_E2_AFEOVvol, // U16 xdata AFEOVvol
_E2_ucRamCheckFlgA, // U8 xdata E2ucRamCheckFlgA
//У׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0B langth=12
_E2_uiVPackGain, //U16 xdata E2uiVPackGain
_E2_siCadcGain, //S16 xdata E2siCadcGain
_E2_siCadcOffset, //S16 xdata E2siCadcOffset
_E2_siTS0Offset, //S16 xdata E2siTS0Offset
_E2_siTS1Offset, //S16 xdata E2siTS1Offset
_E2_ucCalibrated, //S16 xdata E2ucCalibrated
_E2_ucRamCheckFlgB, //U8 xdata E2ucRamCheckFlgB
},
_FLASH_CHECK_DATA, // U16 xdata FlashCheck
};
//*** <<< end of configuration section >>> ***