344 lines
9.2 KiB
C
344 lines
9.2 KiB
C
|
/********************************************************************************
|
|||
|
Copyright (C), Sinowealth Electronic. Ltd.
|
|||
|
Author: Sino
|
|||
|
Version: V0.0
|
|||
|
Date: 2020/04/26
|
|||
|
History:
|
|||
|
V2.0 2020/04/26 Preliminary
|
|||
|
********************************************************************************/
|
|||
|
#include "Main.h"
|
|||
|
|
|||
|
|
|||
|
|
|||
|
/*************************************************************************************************
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: McuTimer3Set
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: ClkSource: <EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD>Ļ<EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD>ֱ<EFBFBD>Ϊ32KHz<EFBFBD><EFBFBD>128KHz<EFBFBD><EFBFBD>24MHz<EFBFBD><EFBFBD>ϵͳʱ<EFBFBD>ӣ<EFBFBD>
|
|||
|
XmS<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><EFBFBD>1000mSʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD><EFBFBD><EFBFBD>1000mSʱ<EFBFBD><EFBFBD>ֻ<EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>32KHz<EFBFBD><EFBFBD>128KHz<EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>Timer3<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>
|
|||
|
*************************************************************************************************/
|
|||
|
void McuTimer3Set(U8 ClkSource, U16 XmS)
|
|||
|
{
|
|||
|
U16 TempVal;
|
|||
|
|
|||
|
McuBank1Sel();
|
|||
|
|
|||
|
// if(ClkSource == TIM_CLK_32KHz)
|
|||
|
// {
|
|||
|
// if(XmS < 1000)
|
|||
|
// {
|
|||
|
// T3CON = 0x02; //<2F>ⲿ32.768kHzΪʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>1<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2S
|
|||
|
// TempVal = (U32)0x10000 - (U32)32.768*XmS;
|
|||
|
// }
|
|||
|
// else
|
|||
|
// {
|
|||
|
// T3CON = 0x22; //<2F>ⲿ32.768kHzΪʱ<EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD>64<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>128s
|
|||
|
// TempVal = 0x10000 - (U32)32.768*XmS/64;
|
|||
|
// }
|
|||
|
// }
|
|||
|
// else if(ClkSource == TIM_CLK_128KHz)
|
|||
|
// {
|
|||
|
// if(XmS < 4000)
|
|||
|
// {
|
|||
|
// T3CON = 0x12; //<2F>ⲿ128kHzΪʱ<CEAA><CAB1>Դ<EFBFBD><D4B4>8<EFBFBD><38>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>4.096S
|
|||
|
// TempVal = 0x10000 - (U32)128*XmS/8;
|
|||
|
// }
|
|||
|
// else
|
|||
|
// {
|
|||
|
// T3CON = 0x32; //<2F>ⲿ128kHzΪʱ<CEAA><CAB1>Դ<EFBFBD><D4B4>256<35><36>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>131.072S
|
|||
|
// TempVal = 0x10000 - (U32)128*XmS/256;
|
|||
|
// }
|
|||
|
// }
|
|||
|
// else if(ClkSource == TIM_CLK_24MHz)
|
|||
|
// {
|
|||
|
// if(XmS < 500)
|
|||
|
// {
|
|||
|
// T3CON = 0x30; //ϵͳ24MHzΪʱ<CEAA><CAB1>Դ<EFBFBD><D4B4>256<35><36>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>669.5ms
|
|||
|
// TempVal = 0x10000 - (U32)24000*XmS/256;
|
|||
|
// }
|
|||
|
// else
|
|||
|
// {
|
|||
|
// T3CON = 0x32; //<2F>ⲿ128kHzΪʱ<CEAA><CAB1>Դ<EFBFBD><D4B4>256<35><36>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>131.072S
|
|||
|
// TempVal = 0x10000 - (U32)128*XmS/256;
|
|||
|
// }
|
|||
|
// }
|
|||
|
|
|||
|
//8MHz<48><7A><EFBFBD><EFBFBD>
|
|||
|
T3CON = 0x30; //ϵͳ8MHzΪʱ<CEAA><CAB1>Դ<EFBFBD><D4B4>256<35><36>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>669.5ms
|
|||
|
TempVal = 0x10000 - (U32)8000*XmS/256;
|
|||
|
|
|||
|
TL3 = TempVal;
|
|||
|
TH3 = TempVal>>8;
|
|||
|
TR3 = 1; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>3
|
|||
|
|
|||
|
McuBank0Sel();
|
|||
|
}
|
|||
|
|
|||
|
|
|||
|
/*************************************************************************************************
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: McuClockSet
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: SysClock<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>ϵͳʱ<EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>AFE
|
|||
|
*************************************************************************************************/
|
|||
|
void McuClockSet(U8 SysClock)
|
|||
|
{
|
|||
|
U8 ea;
|
|||
|
|
|||
|
ea = EA;
|
|||
|
EA = 0;
|
|||
|
|
|||
|
CLKCON |= 0x08; //SETB HFON
|
|||
|
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
|
|||
|
CLKCON &= 0x60;
|
|||
|
|
|||
|
CLKCON |= 0x04; //SETB FS, SYSCLK=24M
|
|||
|
|
|||
|
EA = ea;
|
|||
|
}
|
|||
|
|
|||
|
|
|||
|
/*************************************************************************************************
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: McuPWM0Set<EFBFBD><EFBFBD>McuPWM1Set<EFBFBD><EFBFBD>McuPWM2Set
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: PwmFreq<EFBFBD><EFBFBD>PWM<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD>Hz<EFBFBD><EFBFBD>DutyRatio<EFBFBD><EFBFBD>PWM<EFBFBD>ĸߵ<EFBFBD>ƽռ<EFBFBD>ձ<EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>AFE
|
|||
|
*************************************************************************************************/
|
|||
|
void McuPWM0Set(U16 PwmFreq, U8 DutyRatio)
|
|||
|
{
|
|||
|
PWM0CON = 0xb0; //ϵͳʱ<CDB3><CAB1>/64
|
|||
|
PWM0PL = 375000/PwmFreq; //PWM2P=24000000/(64*E2uiDSG1PWMFreq);
|
|||
|
PWM0PH = (375000/PwmFreq) >> 8;
|
|||
|
PWM0DL = (U16)(PWM0PL+PWM0PH*256)*DutyRatio/100;
|
|||
|
PWM0DH = ((U16)(PWM0PL+PWM0PH*256)*DutyRatio/100) >> 8;
|
|||
|
}
|
|||
|
|
|||
|
void McuPWM1Set(U16 PwmFreq, U8 DutyRatio)
|
|||
|
{
|
|||
|
PWM1CON = 0xb0; //ϵͳʱ<CDB3><CAB1>/64
|
|||
|
PWM1PL = 375000/PwmFreq; //PWM2P=24000000/(64*E2uiDSG1PWMFreq);
|
|||
|
PWM1PH = (375000/PwmFreq) >> 8;
|
|||
|
PWM1DL = (U16)(PWM1PL+(U16)PWM1PH*256)*DutyRatio/100;
|
|||
|
PWM1DH = ((U16)(PWM1PL+(U16)PWM1PH*256)*DutyRatio/100) >> 8;
|
|||
|
}
|
|||
|
|
|||
|
void McuPWM2Set(U16 PwmFreq, U8 DutyRatio)
|
|||
|
{
|
|||
|
PWM2CON = 0xb0; //ϵͳʱ<CDB3><CAB1>/64
|
|||
|
PWM2PL = 375000/PwmFreq; //PWM2P=24000000/(64*E2uiDSG1PWMFreq);
|
|||
|
PWM2PH = (375000/PwmFreq) >> 8;
|
|||
|
PWM2DL = (U16)(PWM2PL+(U16)PWM2PH*256)*DutyRatio/100;
|
|||
|
PWM2DH = ((U16)(PWM2PL+(U16)PWM2PH*256)*DutyRatio/100) >> 8;
|
|||
|
}
|
|||
|
|
|||
|
|
|||
|
/*************************************************************************************************
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: Delay1ms
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: Xms<EFBFBD><EFBFBD><EFBFBD>ӳٶ<EFBFBD><EFBFBD><EFBFBD>mS
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λΪ1mS
|
|||
|
<EFBFBD>ر<EFBFBD>ע<EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱȷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>⣬<EFBFBD>ڲ<EFBFBD>ͬ<EFBFBD>Ż<EFBFBD><EFBFBD>ȼ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD>һ<EFBFBD>£<EFBFBD>ʵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>£<EFBFBD>
|
|||
|
1.<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ż<EFBFBD><EFBFBD>ȼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ3ʱ<EFBFBD><EFBFBD>j=1670<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϣ<EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱΪ3.484ms<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD>ж<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>Ӱ<EFBFBD>죬<EFBFBD>ﵽ3.804ms
|
|||
|
2.<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ż<EFBFBD><EFBFBD>ȼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ3ʱ<EFBFBD><EFBFBD>j=480<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϣ<EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱΪ1.010ms<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD>ж<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>Ӱ<EFBFBD>죬<EFBFBD>ﵽ1.104ms
|
|||
|
3.<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ż<EFBFBD><EFBFBD>ȼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ7ʱ<EFBFBD><EFBFBD>j=1670<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϣ<EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱΪ1.002ms<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD>ж<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>Ӱ<EFBFBD>죬<EFBFBD>ﵽ1.090ms
|
|||
|
*************************************************************************************************/
|
|||
|
void Delay1ms(U8 Xms)
|
|||
|
{
|
|||
|
U8 i;
|
|||
|
U16 j, Tcnt;
|
|||
|
|
|||
|
if((CLKCON&0x70) == MCU_CLK_24MHz)
|
|||
|
{
|
|||
|
Tcnt = 1670;
|
|||
|
}
|
|||
|
else if((CLKCON&0x70) == MCU_CLK_12MHz)
|
|||
|
{
|
|||
|
Tcnt = 1670/2;
|
|||
|
}
|
|||
|
else if((CLKCON&0x70) == MCU_CLK_6MHz)
|
|||
|
{
|
|||
|
Tcnt = 1670/4;
|
|||
|
}
|
|||
|
else //2MHz
|
|||
|
{
|
|||
|
Tcnt = 1670/12;
|
|||
|
}
|
|||
|
|
|||
|
|
|||
|
for(i=0; i<Xms; i++) //system clock = 24MHz
|
|||
|
{
|
|||
|
for(j=0; j<Tcnt; j++)
|
|||
|
{
|
|||
|
}
|
|||
|
}
|
|||
|
}
|
|||
|
|
|||
|
|
|||
|
|
|||
|
/*************************************************************************************************
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: ClrRam
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD><EFBFBD><EFBFBD>DATA<EFBFBD><EFBFBD>IDATA<EFBFBD><EFBFBD>XRAM<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ջ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
*************************************************************************************************/
|
|||
|
//void ClrRam(void)
|
|||
|
//{
|
|||
|
// U8 idata *ptr1;
|
|||
|
// U8 xdata *ptr2;
|
|||
|
// U8 xdata i;
|
|||
|
// U16 idata j;
|
|||
|
|
|||
|
// for(i=0x08; i<=STACK_ADDR-1; i++) //clear ram address: 08H~STACK_ADDR-1
|
|||
|
// {
|
|||
|
// ptr1 = (U8 idata *)i;
|
|||
|
// *ptr1 = 0;
|
|||
|
// }
|
|||
|
|
|||
|
// for(j=0; j<=0xAFF; j++) //clear XDATA address:0000H-0AFFH
|
|||
|
// {
|
|||
|
// ptr2 = (U8 xdata *)j;
|
|||
|
// *ptr2 = 0;
|
|||
|
// }
|
|||
|
//}
|
|||
|
|
|||
|
|
|||
|
/*************************************************************************************************
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: RamCheckProcess
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵͳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>XRAM<EFBFBD><EFBFBD><EFBFBD>ı<EFBFBD>־<EFBFBD>Ƿ<EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>
|
|||
|
*************************************************************************************************/
|
|||
|
BOOL RamCheckProcess(void)
|
|||
|
{
|
|||
|
if((E2ucRamCheckFlg0 != RAM_CHECK_DATA)
|
|||
|
|| (E2ucRamCheckFlg1 != RAM_CHECK_DATA)
|
|||
|
|| (E2ucRamCheckFlg2 != RAM_CHECK_DATA)
|
|||
|
|| (E2ucRamCheckFlg3 != RAM_CHECK_DATA)
|
|||
|
|| (E2ucRamCheckFlg5 != RAM_CHECK_DATA)
|
|||
|
|| (E2ucRamCheckFlg6 != RAM_CHECK_DATA)
|
|||
|
|| (E2ucRamCheckFlg7 != RAM_CHECK_DATA)
|
|||
|
|| (E2ucRamCheckFlg8 != RAM_CHECK_DATA)
|
|||
|
|| (E2ucRamCheckFlg9 != RAM_CHECK_DATA)
|
|||
|
|| (E2ucRamCheckFlgA != RAM_CHECK_DATA)
|
|||
|
|| (E2ucRamCheckFlgB != RAM_CHECK_DATA)
|
|||
|
|| (E2uiCheckFlag != 0x5AA5))
|
|||
|
{
|
|||
|
return 0;
|
|||
|
}
|
|||
|
else
|
|||
|
{
|
|||
|
return 1;
|
|||
|
}
|
|||
|
}
|
|||
|
|
|||
|
|
|||
|
/*************************************************************************************************
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: MemorySet
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: pt--memoryָ<EFBFBD><EFBFBD>
|
|||
|
setval---<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD>ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
length---<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD>ֵ<EFBFBD><EFBFBD>memory<EFBFBD><EFBFBD><EFBFBD><EFBFBD>(Byres)
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵͳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>XRAM<EFBFBD><EFBFBD><EFBFBD>ı<EFBFBD>־<EFBFBD>Ƿ<EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>
|
|||
|
*************************************************************************************************/
|
|||
|
void MemorySet(U8 xdata *pt, U8 setval, U8 length)
|
|||
|
{
|
|||
|
U8 i;
|
|||
|
for(i=0; i<length; i++)
|
|||
|
{
|
|||
|
*pt = setval;
|
|||
|
pt++;
|
|||
|
}
|
|||
|
}
|
|||
|
|
|||
|
|
|||
|
/*************************************************************************************************
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: MemoryCopy
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: source--ԴMemoryָ<EFBFBD><EFBFBD>
|
|||
|
target---Ŀ<EFBFBD><EFBFBD>Memoryָ<EFBFBD><EFBFBD>
|
|||
|
length---<EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><EFBFBD><EFBFBD>(Byres)
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵͳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>XRAM<EFBFBD><EFBFBD><EFBFBD>ı<EFBFBD>־<EFBFBD>Ƿ<EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>
|
|||
|
*************************************************************************************************/
|
|||
|
void MemoryCopy(U8 xdata *source, U8 xdata *target, U8 length)
|
|||
|
{
|
|||
|
U8 i;
|
|||
|
for(i=0; i<length; i++)
|
|||
|
{
|
|||
|
*target = *source;
|
|||
|
target++;
|
|||
|
source++;
|
|||
|
}
|
|||
|
}
|
|||
|
|
|||
|
|
|||
|
/*************************************************************************************************
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: McuIntoIdle<EFBFBD><EFBFBD>McuIntoPD
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: MCU<EFBFBD><EFBFBD><EFBFBD><EFBFBD>PD<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>IDLEģʽ<EFBFBD><EFBFBD><EFBFBD>Խ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
*************************************************************************************************/
|
|||
|
void McuIntoIdle(void)
|
|||
|
{
|
|||
|
SUSLO = 0x55;
|
|||
|
PCON |= 0x01;
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
}
|
|||
|
|
|||
|
void McuIntoPD(void)
|
|||
|
{
|
|||
|
SUSLO = 0x55;
|
|||
|
PCON |= 0x02;
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
_nop_();
|
|||
|
}
|
|||
|
|
|||
|
|
|||
|
/*************************************************************************************************
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>: SystemResetProcess
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ: <EFBFBD><EFBFBD>
|
|||
|
* <EFBFBD><EFBFBD> <EFBFBD><EFBFBD>: ϵͳ<EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD>ӳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>ַ<EFBFBD><EFBFBD>ʼִ<EFBFBD><EFBFBD>
|
|||
|
*************************************************************************************************/
|
|||
|
void SystemResetProcess(void)
|
|||
|
{
|
|||
|
if( (ucResetFlag==0x12) && (bUart0SndAckFlg||bUart1SndAckFlg||bUart2SndAckFlg) //Software reset occurs, and ended UART communication
|
|||
|
&& (!bMcuFlashWrWaitFlg) && (!bMcuFlashWrFlg) ) //Flash has been updated
|
|||
|
{
|
|||
|
IrqDis();
|
|||
|
IEN0 = 0x00; //Disable Interrupt
|
|||
|
IEN1 = 0x00;
|
|||
|
TCON = 0x00;
|
|||
|
EXF0 = 0x00;
|
|||
|
|
|||
|
SBRTH = 0x00; //Disable UART0
|
|||
|
SBRTL = 0x00;
|
|||
|
SCON = 0x00;
|
|||
|
|
|||
|
((void(code*)(void))0x0000)(); //ָ<><D6B8><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
|
|||
|
}
|
|||
|
}
|
|||
|
|
|||
|
|
|||
|
|
|||
|
|
|||
|
|
|||
|
|
|||
|
|
|||
|
|