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修改Flash默认电池串数
2025-02-08 07:27:19 +00:00
C51 COMPILER V9.01 DATAFLASH 02/08/2025 14:58:02 PAGE 1
First commit
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C51 COMPILER V9.01, COMPILATION OF MODULE DATAFLASH
OBJECT MODULE PLACED IN .\output\DataFlash.obj
COMPILER INVOKED BY: D:\Tool\Keil\C51\BIN\C51.EXE code_dataflash\DataFlash.c LARGE OPTIMIZE(7,SIZE) BROWSE INCDIR(.\head
-er) DEBUG OBJECTEXTEND PRINT(.\output\DataFlash.lst) OBJECT(.\output\DataFlash.obj)
line level source
1 /********************************************************************************
2 Copyright (C), Sinowealth Electronic. Ltd.
3 Author: Sino
4 Version: V0.0
5 Date: 2014/09/10
6 History:
7 V0.0 2014/09/10 Preliminary
8 ********************************************************************************/
9 //*** <<< use Configuration Wizard in Context Menu >>> ***
10 #define _RAM_CHECK_DATA 0x5A
11 #define _FLASH_CHECK_DATA 0x5AA5
12
13 // <h> ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2>(SubClassID=0x00 length=48)
14 // <h> <20><><EFBFBD>ذ<EFBFBD><D8B0><EFBFBD>Ϣ<EFBFBD><CFA2>E2uiPackConfigMap<61><70>
15 // <q> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
16 #define _EPCM_LOAD_LOCK 0 //BIT15; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD>ܸ<EFBFBD><DCB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>; 1<><31>ʹ<EFBFBD>ܸ<EFBFBD><DCB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
17 // <q> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
18 #define _EPCM_CHARGER_LOCK 0 //BIT14; 0<><30><EFBFBD><EFBFBD>֧<EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>; 1<><31>֧<EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
19 // <q> <20>¶ȼ<C2B6><C8BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
20 #define _EPCM_TEMP_NUM 1 //BIT13; 0<><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¶ȼ<C2B6><C8BC><EFBFBD><EFBFBD><EFBFBD> 1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>¶ȼ<C2B6><C8BC><EFBFBD><EFBFBD><EFBFBD>
21 // <o> LED<45><44>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD>
22 #define _EPCM_LED_NUM 0 //BIT11~12; δ<><CEB4><EFBFBD><EFBFBD>
23 // <o> <20><>о<EFBFBD><D0BE><EFBFBD><EFBFBD>
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24 #define _EPCM_CELL_NUM 4 //BIT8~10; <20><>о<EFBFBD><D0BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>6~10<31><30>
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25 // <q> <20><><EFBFBD><EFBFBD>EEPROM<4F><4D><EFBFBD><EFBFBD>
26 #define _EPCM_EEPROM_EN 0 //BIT7; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>EE<45><45><EFBFBD>ݹ<EFBFBD><DDB9><EFBFBD>; 1<><31>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>EE<45><45><EFBFBD>ݹ<EFBFBD><DDB9><EFBFBD>
27 // <q> <20>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>MOS<4F><53><EFBFBD><EFBFBD>
28 #define _EPCM_OCPM 0 //BIT6; δ<><CEB4><EFBFBD>ã<EFBFBD>0<EFBFBD><30><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>رշŵ<D5B7>mos 1<><31><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>رճ<D8B1><D5B3>ŵ<EFBFBD>mos<6F><73>
29 // <q> <20><><EFBFBD>߼<EFBFBD><DFBC><EFBFBD>
30 #define _EPCM_CTO_EN 1 //BIT5; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD>ܶ<EFBFBD><DCB6>߱<EFBFBD><DFB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>; 1<><31>ʹ<EFBFBD>ܶ<EFBFBD><DCB6>߱<EFBFBD><DFB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
-
31 // <q> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
32 #define _EPCM_PF_EN 1 //BIT4; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD>ܶ<EFBFBD><DCB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>; 1<><31>ʹ<EFBFBD>ܶ<EFBFBD><DCB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
33 // <q> <20><><EFBFBD><EFBFBD>
34 #define _EPCM_BAL_EN 0 //BIT3; 0<><30><EFBFBD><EFBFBD>ʹ<EFBFBD>ܾ<EFBFBD><DCBE>⹦<EFBFBD>ܣ<EFBFBD> 1<><31>ʹ<EFBFBD>ܾ<EFBFBD><DCBE>⹦<EFBFBD><E2B9A6>
35 // <q> <20><><EFBFBD><EFBFBD><EFBFBD>Իָ<D4BB>
36 #define _EPCM_OCRC_EN 0 //BIT2; 0:<3A><>ʹ<EFBFBD>ܹ<EFBFBD><DCB9><EFBFBD><EFBFBD>Իָ<D4BB><D6B8><EFBFBD><EFBFBD>ܣ<EFBFBD> 1<><31>ʹ<EFBFBD>ܹ<EFBFBD><DCB9><EFBFBD><EFBFBD>Իָ<D4BB><D6B8><EFBFBD><EFBFBD><EFBFBD>
37 // <q> Ӳ<><D3B2><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD>
38 #define _EPCM_OV_EN 1 //BIT1; 0:<3A><>ʹ<EFBFBD><CAB9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD>ܣ<EFBFBD> 1<><31>ʹ<EFBFBD><CAB9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD>
39 // <q> Ӳ<><D3B2><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD>
40 #define _EPCM_SC 1 //BIT0; 0:<3A><>ʹ<EFBFBD><CAB9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD> 1<><31>ʹ<EFBFBD><CAB9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
41
42 #define _E2_PACKCONFIGMAP (_EPCM_EEPROM_EN<<15)|(_EPCM_OCPM<<14)|(_EPCM_CTO_EN<<13)|(_EPCM_PF_EN<<12)
-\
43 |(_EPCM_BAL_EN<<11)|(_EPCM_OCRC_EN<<10)|(_EPCM_OV_EN<<9)\
44 |(_EPCM_SC<<8)|(_EPCM_LOAD_LOCK<<7)|(_EPCM_CHARGER_LOCK<<6)\
45 |(_EPCM_TEMP_NUM<<5)|(_EPCM_LED_NUM<<4)|(_EPCM_CELL_NUM-3) //U16 xdata E2uiPackConfigMap
46
47 // </h>
48
49 // <h>OCV<43><56>ѹ<EFBFBD><D1B9>mV<6D><56>
50 // <o>10%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
51 #define _E2_VOC10 3200 //U16 xdata VOC10
52 // <o>20%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
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53 #define _E2_VOC20 3400 //U16 xdata VOC10
54 // <o>30%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
55 #define _E2_VOC30 3550 //U16 xdata VOC10
56 // <o>40%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
57 #define _E2_VOC40 3700 //U16 xdata VOC10
58 // <o>50%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
59 #define _E2_VOC50 3800 //U16 xdata VOC10
60 // <o>60%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
61 #define _E2_VOC60 3900 //U16 xdata VOC10
62 // <o>70%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
63 #define _E2_VOC70 4000 //U16 xdata VOC10
64 // <o>80%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
65 #define _E2_VOC80 4100 //U16 xdata VOC10
66 // <o>90%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
67 #define _E2_VOC90 4150 //U16 xdata VOC10
68 // <o>100%<25><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ѹ
69 #define _E2_VOC100 4200 //U16 xdata VOC10
70 // </h>
71
72 // <h><3E><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ԥ<EFBFBD><D4A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
73 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>mAh<41><68>
74 #define _E2_ulDesignCapacity 4000 //U32 xdata E2ulDesignCapacity
75 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>mAh<41><68>
76 #define _E2_ulFCC 4000 //U32 xdata E2ulFCC
77 // <o>ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
78 #define _E2_ulCycleThreshold 3000 // U32 xdata E2ulCycleThreshold
79 // <o>ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
80 #define _E2_uiCycleCount 0 // U16 xdata E2uiCycleCount
81 // <o><3E><><EFBFBD><EFBFBD>ѧϰ<D1A7><EFBFBD>
82 #define _E2_uiLearnLowTempe 2881 // U16 xdata E2uiLearnLowTempe
83 #define _E2_Reserve 0 // U16 xdata E2Reserve Ԥ<><D4A4>ռλ
84 // <o><3E><><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
85 #define _E2_siDfilterCur 100 // U16 xdata E2siDfilterCur
86 // <o><3E>͹<EFBFBD><CDB9>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD>ʱ
87 #define _E2_ucLowPowerDeley 20 // U16 xdata E2ucLowPowerDeley
88 // <o><3E><><EFBFBD>籸<EFBFBD>ݼ<EFBFBD><DDBC><EFBFBD><EFBFBD><EFBFBD>ʱ
89 #define _E2_ucChgBKDelay 1 // U16 xdata E2ucChgBKDelay
90 // <o><3E><><EFBFBD>籸<EFBFBD>ݼ<EFBFBD><DDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
91 #define _E2_siChgBKCur 100 // U16 xdata E2siChgBKCur
92 // <o>RTC<54><43><EFBFBD>ݼ<EFBFBD><DDBC><EFBFBD><EFBFBD><EFBFBD>ʱ
93 #define _E2_ucRTCBKDelay 5 // U16 xdata E2ucRTCBKDelay
94 #define _E2_ucRamCheckFlg0 _RAM_CHECK_DATA // U16 xdata E2ucRamCheckFlg0
95 // </h>
96 // </h>
97
98 // <h><3E>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x01 length=50)
99 // <o><3E><><EFBFBD><EFBFBD><EFBFBD>汾(EXP:0x0106 = V1.06)<0x0000-0xffff>
100 #define _E2_SWVersion 0x0215 // U16 xdata SWVersion
101 // <o>Ӳ<><D3B2><EFBFBD>汾(EXP:0x0106 = V1.06)<0x0000-0xffff>
102 #define _E2_HWVersion 0x0130 // U16 xdata HWVersion
103 // <o><3E>豸ID<0x00-0xff>
104 #define _E2_ID 0x00 // U8 xdata ID
105 // <s.12><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
106 #define _E2_MNFName "sinowealth" // U8 xdata MNFName[12]
107 // <o> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>exp<78><70>0x20230404=2023.04.04<EFBFBD><EFBFBD><0x00000000-0xffffffff>
108 #define _E2_MNFDate 0x20231222 // U32 xdata MNFDate
109 // <o><3E><><EFBFBD>к<EFBFBD><0x0000-0xffff>
110 #define _E2_SerialNum 0x0000 // U16 xdata SerialNum
111 // <s.12><3E>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD>
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112 #define _E2_DeviceName "SH39F003" // U8 xdata DeviceName[12]
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113 // <s.4><3E><>о<EFBFBD><D0BE><EFBFBD><EFBFBD>
114 #define _E2_DeviceChem "LION" // U8 xdata DeviceChem[12]
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115 // <o><3E><>о<EFBFBD><D0BE>ѧID<0x0000-0xffff>
116 #define _E2_ChemID 0x0000 // U16 xdata ChemID
117 #define _E2_ucRamCheckFlg1 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg2
118 // </h>
119
120 // <h><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x02 length=18)
121 // <o><3E><>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
122 #define _E2_uiOVvol 4250 // U16 xdata E2uiOVvol
123 // <o><3E><>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ֵ
124 #define _E2_uiOVRvol 4150 // U16 xdata E2uiOVRvol
125 // <o><3E><>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ
126 #define _E2_ucDelayOV 2 // U8 xdata E2ucDelayOV
127 // <o><3E><>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ʱ
128 #define _E2_ucDelayOVR 2 // U8 xdata E2ucDelayOVR
129 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><D6B9>ѹ(mV)
130 #define _E2_uiChgEndVol 4160 // U16 xdata E2uiChgEndVol
131 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>(mA)
132 #define _E2_siChgEndCurr 100 // S16 xdata E2siChgEndCurr
133 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><D6B9>ʱ(S)
134 #define _E2_ucChgEndDelay 5 // U8 xdata E2ucChgEndDelay
135 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
136 #define _E2_slOCCvol 3000 // U32 xdata E2slOCCvol
137 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ
138 #define _E2_ucDelayOCC 2 // U8 xdata E2ucDelayOCC
139 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ʱ
140 #define _E2_ucDelayOCCR 2 // U8 xdata E2ucDelayOCCR
141 #define _E2_ucRamCheckFlg2 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg2
142 // </h>
143
144 // <h><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x03 length=21)
145 // <o>Ƿѹ<C7B7><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ
146 #define _E2_uiUVvol 2700 // U16 xdata E2uiUVvol
147 // <o>Ƿѹ<C7B7><D1B9><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ѹ
148 #define _E2_uiUVRvol 3000 // U16 xdata E2uiUVRvol
149 // <o>Ƿѹ<C7B7><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ
150 #define _E2_ucDelayUV 2 // U8 xdata E2ucDelayUV
151 // <o>Ƿѹ<C7B7><D1B9><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ʱ
152 #define _E2_ucDelayUVR 2 // U8 xdata E2ucDelayUVR
153 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD>ֹ<EFBFBD><D6B9>ʱ(S)
154 #define _E2_ucDsgEndDelay 5 // U8 xdata E2ucDsgEndDelay
155 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD>ֹ<EFBFBD><D6B9>ѹ(mV)
156 #define _E2_uiDsgEndVol 2900 // U16 xdata E2uiDsgEndVol
157 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
158 #define _E2_uiOCDvol -20000 //U32 xdata E2uiOCDvol
159 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ
160 #define _E2_ucDelayOCD 2 //U8 xdata E2ucDelayOCD
161 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
162 #define _E2_slOCD2vol -40000 // S32 xdata E2slOCD2vol
163 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ
164 #define _E2_ucDelayOCD2 2 //U8 xdata E2ucDelayOCD2
165 // <o><3E><><EFBFBD><EFBFBD><EFBFBD>Ƴ<EFBFBD><C6B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ
166 #define _E2_ucDelayLoadR 4 //U8 xdata E2ucDelayLoadR
167 #define _E2_ucRamCheckFlg3 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg3
168 // </h>
169
170 // <h><3E>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD>(SubClassID=0x05 length=5)
171 // <o>PWMƵ<4D><C6B5>(Hz)
172 #define _E2_DSG1PWMFreq 4000 // U16 xdata DSG1PWMFreq
173 // <o>PWM<57>͵<EFBFBD>ռ<EFBFBD>ձ<EFBFBD>(%)
174 #define _E2_DSG1PWMRatioL 30 // U8 xdata DSG1PWMRatioL
175 // <o>PWM<57>ߵ<EFBFBD>ռ<EFBFBD>ձ<EFBFBD>(%)
176 #define _E2_DSG1PWMRatioH 70 // U8 xdata DSG1PWMRatioH
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177 #define _E2_ucRamCheckFlg5 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg5
178 // </h>
179
180 // <h><3E><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x06 length=11)
181 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>(_E2_TempOTC=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*10+2731)
182 #define _E2_TempOTC 3231 // U16 xdata TempOTC
183 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>(_E2_TempOTCR=<3D>ͷ<EFBFBD><CDB7><EFBFBD>*10+2731)
184 #define _E2_TempOTCR 3181 // U16 xdata TempOTCR
185 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>(_E2_TempUTC=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*10+2731)
186 #define _E2_TempUTC 2731 // U16 xdata TempUTC
187 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>(_E2_TempUTCR=<3D>ͷ<EFBFBD><CDB7><EFBFBD>*10+2731)
188 #define _E2_TempUTCR 2781 // U16 xdata TempUTCR
189 // <o><3E>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD>ʱ(s)
190 #define _E2_DelayOTC 3 // U8 xdata DelayOTC
191 // <o><3E>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>ʱ(s)
192 #define _E2_DelayOTCR 3 // U8 xdata DelayOTCR
193 #define _E2_ucRamCheckFlg6 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg6
194 // </h>
195
196 // <h><3E>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x07 length=9)
197 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>(_E2_TempOTC=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*10+2731)
198 #define _E2_TempOTD 3431 // U16 xdata TempOTD
199 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>(_E2_TempOTCR=<3D>ͷ<EFBFBD><CDB7><EFBFBD>*10+2731)
200 #define _E2_TempOTDR 3281 // U16 xdata TempOTDR
201 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD>(_E2_TempUTC=<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*10+2731)
202 #define _E2_TempUTD 2631 // U16 xdata TempUTD
203 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>(_E2_TempUTCR=<3D>ͷ<EFBFBD><CDB7><EFBFBD>*10+2731)
204 #define _E2_TempUTDR 2681 // U16 xdata TempUTDR
205 #define _E2_ucRamCheckFlg7 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg6
206 // </h>
207
208 // <h>ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(SubClassID=0x08 length=8)
209 // <o>ƽ<><C6BD><EFBFBD><EFBFBD>ѹ(mV)
210 #define _E2_BalanceVol 4180 // U16 xdata BalanceVol
211 // <o>ƽ<><C6BD>ѹ<EFBFBD><D1B9>(mV)
212 #define _E2_BalanceVolDiff 20 // U16 xdata BalanceVolDiff
213 // <o>ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(mA)
214 #define _E2_BalCurrent 100 // S16 xdata BalCurrent
215 // <o>ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ(S)
216 #define _E2_BalanceDelay 2 // U8 xdata BalanceDelay
217 #define _E2_ucRamCheckFlg8 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg8
218 // </h>
219
220 // <h><3E><><EFBFBD><EFBFBD>ͳ<EFBFBD>Ʋ<EFBFBD><C6B2><EFBFBD>(SubClassID=0x09 length=17)
221 // <o><3E><><EFBFBD><EFBFBD><EFBFBD>ٷֱ<D9B7>SOC(%)
222 #define _E2_ucSOC 100 // U8 xdata E2ucSOC
223 // <o>ʣ<><CAA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>E2ulDfRC(mAh)
224 #define _E2_ulDfRC 3000 // U32 xdata E2ulLastFCC
225 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>
226 #define _E2_slDsgEndCurr -5000 // U32 xdata E2slDsgEndCurr
227 // <o><3E>ŵ<EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
228 #define _E2_ulCycleThresholdCount 0 // U32 xdata E2ulCycleThresholdCount
229 // <o><3E>ϴθ<CFB4><CEB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
230 #define _E2_uiLastCCount 0 // U16 xdata E2uiLastCCount
231 // <o><3E>ŵ<EFBFBD><C5B5><EFBFBD>ֹ<EFBFBD><D6B9>־
232 #define _E2_ucDsgEndFlg 0 //U8 xdata E2ucDsgEndFlg
233 #define _E2_ucRamCheckFlg9 _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlg9
234 // </h>
235
236 // <h>AFE<46><45><EFBFBD><EFBFBD>(SubClassID=0x0A length=4)
237 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
238 #define _E2_AFEProtectConfig 0x74 // U8 xdata AFEProtectConfig
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239 // <o>Ӳ<><D3B2><EFBFBD><EFBFBD>ѹ<EFBFBD><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
240 #define _E2_AFEOVvol 4400 // U16 xdata AFEOVvol
241 #define _E2_ucRamCheckFlgA _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlgA
242 // </h>
243
244 // <h>У׼<D0A3><D7BC><EFBFBD><EFBFBD>(SubClassID=0x0B length=12)
245 // <o><3E><>ѹУ׼<D0A3><D7BC><EFBFBD><EFBFBD>
246 #define _E2_uiVPackGain 2594 // U16 xdata E2uiVPackGain
247 // <o><3E><><EFBFBD><EFBFBD>У׼<D0A3><D7BC><EFBFBD><EFBFBD>
248 #define _E2_siCadcGain -82 // S16 xdata E2siCadcGain
249 // <o><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ư
250 #define _E2_siCadcOffset 1 // S16 xdata E2siCadcOffset
251 // <o><3E>ⲿ<EFBFBD><EFBFBD><C2B6><EFBFBD>Ư(TS0)
252 #define _E2_siTS0Offset 0 // S16 xdata E2siTS0Offset
253 // <o><3E>ⲿ<EFBFBD><EFBFBD><C2B6><EFBFBD>Ư(TS1)
254 #define _E2_siTS1Offset 0 // S16 xdata E2siTS1Offset
255 // <o>У׼<D0A3><D7BC><EFBFBD><EFBFBD>Ԥ<EFBFBD><D4A4>
256 #define _E2_ucCalibrated 0 // U8 xdata E2ucCalibrated
257 #define _E2_ucRamCheckFlgB _RAM_CHECK_DATA // U8 xdata E2ucRamCheckFlgB
258 // </h>
259
260 /*********************************************************************************************************
-********/
261 /*********************************************************************************************************
-********/
262 /*********************************************************************************************************
-********/
263 /*********************************************************************************************************
-********/
264 /*********************************************************************************************************
-********/
265 /*********************************************************************************************************
-********/
266 /*********************************************************************************************************
-********/
267 /*********************************************************************************************************
-********/
268 /*********************************************************************************************************
-********/
269 /*********************************************************************************************************
-********/
270 /*********************************************************************************************************
-********/
271 /*********************************************************************************************************
-********/
272
273 struct DataFlashStu
274 {
275 //ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʼ SubClassID=0x00 length=48
276 unsigned int E2uiPackConfigMap;
277 unsigned int E2uiVOC[10];
278 unsigned long E2ulDesignCapacity;
279 unsigned long E2ulFCC;
280 unsigned long E2ulCycleThreshold;
281 unsigned int E2uiCycleCount;
282 unsigned int E2uiLearnLowTempe;
283 unsigned int E2Reserve;
284 signed int E2siDfilterCur;
285 unsigned char E2ucLowPowerDeley;
286 unsigned char E2ucChgBKDelay;
287 unsigned int E2siChgBKCur;
288 unsigned char E2ucRTCBKDelay;
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289 unsigned char E2ucRamCheckFlg0;
290
291 //<2F>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x01 langth=50
292 unsigned int E2uiSWVersion;
293 unsigned int E2uiHWVersion;
294 unsigned char E2ucID;
295 unsigned char E2ucMNFName[12];
296 unsigned long E2ulMNFDate;
297 unsigned int E2uiSerialNum;
298 unsigned char E2ucDeviceName[12];
299 unsigned char E2ucDeviceChem[12];
300 unsigned int E2uiChemID;
301 unsigned char E2ucRamCheckFlg1;
302
303 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x02 langth=18
304 unsigned int E2uiOVvol;
305 unsigned int E2uiOVRvol;
306 unsigned char E2ucOVDelay;
307 unsigned char E2ucOVRDelay;
308 unsigned int E2uiChgEndVol0;
309 signed int E2siChgEndCurr0;
310 unsigned char E2ucChgEndDelay0;
311 signed long E2slOCCvol;
312 unsigned char E2ucDelayOCC;
313 unsigned char E2ucDelayOCCR;
314 unsigned char E2ucRamCheckFlg2;
315
316 //<2F>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x03 langth=21
317 unsigned int E2uiUVvol;
318 unsigned int E2uiUVRvol;
319 unsigned char E2ucDelayUV;
320 unsigned char E2ucDelayUVR;
321 unsigned int E2uiDsgEndVol;
322 unsigned char E2ucDsgEndDelay;
323 signed long E2uiOCDvol;
324 unsigned char E2ucDelayOCD;
325 signed long E2slOCD2vol;
326 unsigned char E2ucDelayOCD2;
327 unsigned char E2ucDelayLoadR;
328 unsigned char E2ucRamCheckFlg3;
329
330 //<2F>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x05 langth=5
331 unsigned int DSG1PWMFreq;
332 unsigned char DSG1PWMRatioL;
333 unsigned char DSG1PWMRatioH;
334 unsigned char E2ucRamCheckFlg5;
335
336
337 //<2F><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x06 langth=11
338 unsigned int TempOTC;
339 unsigned int TempOTCR;
340 unsigned int TempUTC;
341 unsigned int TempUTCR;
342 unsigned char DelayOTC;
343 unsigned char DelayOTCR;
344 unsigned char E2ucRamCheckFlg6;
345
346 //<2F>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x07 langth=9
347 unsigned int TempOTD;
348 unsigned int TempOTDR;
349 unsigned int TempUTD;
350 unsigned int TempUTDR;
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351 unsigned char E2ucRamCheckFlg7;
352
353 //ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x08 langth=8
354 unsigned int BalanceVol;
355 unsigned int BalanceVolDiff;
356 unsigned int BalCurrent;
357 unsigned char BalanceDelay;
358 unsigned char E2ucRamCheckFlg8;
359
360 //<2F><><EFBFBD><EFBFBD>ͳ<EFBFBD><CDB3> SubClassID=0x09 length=17
361 unsigned char E2ucSOC;
362 unsigned long E2ulDfRC;
363 signed long E2slDsgEndCurr;
364 unsigned long E2ulCycleThresholdCount;
365 unsigned int E2uiLastCCount;
366 unsigned char E2ucDsgEndFlg;
367 unsigned char E2ucRamCheckFlg9;
368
369 //AFE<46><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0A length=4
370 unsigned char AFEProtectConfig;
371 unsigned int AFEOVvol;
372 unsigned char E2ucRamCheckFlgA;
373
374 //У׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0B length=12
375 unsigned int E2uiVPackGain;
376 signed int E2siCadcGain;
377 unsigned int E2siCadcOffset;
378 unsigned int E2siTS0Offset;
379 unsigned int E2siTS1Offset;
380 unsigned char E2ucCalibrated;
381 unsigned char E2ucRamCheckFlgB;
382 };
383
384 union DataFlashUn
385 {
386 struct DataFlashStu DataFlashStu0; /*һ<><D2BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ṹ<EFBFBD><E1B9B9><EFBFBD>ٶ<EFBFBD><D9B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
387 unsigned char reversed[510];
388 };
389
390 struct DataFlashStr
391 {
392 union DataFlashUn DataFlashUnRaw;
393 unsigned int FlashCheck1;
394 union DataFlashUn DataFlashUnBak;
395 unsigned int FlashCheck2;
396 };
397
398 struct DataFlashStr code dataflashstr =
399 {
400 /*********************************************************************************************************
-********/
401 //<2F><><EFBFBD><EFBFBD>A<EFBFBD><41>
402 /*********************************************************************************************************
-********/
403 //ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʼ SubClassID=0x00 length=48
404 {
405 _E2_PACKCONFIGMAP, //U16 xdata E2uiPackConfigMap
406 _E2_VOC10, //U16 xdata VOC10
407 _E2_VOC20, //U16 xdata VOC20
408 _E2_VOC30, //U16 xdata VOC30
409 _E2_VOC40, //U16 xdata VOC40
410 _E2_VOC50, //U16 xdata VOC50
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411 _E2_VOC60, //U16 xdata VOC60
412 _E2_VOC70, //U16 xdata VOC70
413 _E2_VOC80, //U16 xdata VOC80
414 _E2_VOC90, //U16 xdata VOC90
415 _E2_VOC100, //U16 xdata VOC100
416 _E2_ulDesignCapacity, // U32 xdata E2ulDesignCapacity
417 _E2_ulFCC, // U32 xdata E2ulFCC
418 _E2_ulCycleThreshold, // U32 xdata E2uiCycleThreshold
419 _E2_uiCycleCount, // U16 xdata E2uiCycleCount
420 _E2_uiLearnLowTempe, // U16 xdata E2uiLearnLowTempe
421 _E2_Reserve, // U16 xdata E2Reserve
422 _E2_siDfilterCur, // S16 xdata E2siDfilterCur
423 _E2_ucLowPowerDeley, // U8 xdata E2ucLowPowerDeley
424 _E2_ucChgBKDelay, // U8 xdata E2ucChgBKDelay
425 _E2_siChgBKCur, // S16 xdata E2siChgBKCur
426 _E2_ucRTCBKDelay, // U8 xdata E2ucRTCBKDelay
427 _E2_ucRamCheckFlg0, // U8 xdata E2ucRamCheckFlg0
428
429
430 //<2F>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x01 length=50
431 _E2_SWVersion, //U16 xdata SWVersion
432 _E2_HWVersion, //U16 xdata HWVersion
433 _E2_ID, //U8 xdata ID
434 _E2_MNFName, //U8 xdata MNFName[12]
435 _E2_MNFDate, //U32 xdata MNFDate
436 _E2_SerialNum, //U16 xdata SerialNum
437 _E2_DeviceName, //U8 xdata DeviceName[12]
438 _E2_DeviceChem, //U8 xdata DeviceChem[12]
439 _E2_ChemID, //U16 xdata ChemID
440 _E2_ucRamCheckFlg1, //U8 xdata E2ucRamCheckFlg1
441
442 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x02 length=18
443 _E2_uiOVvol, //U16 xdata E2uiOVvol
444 _E2_uiOVRvol, //U16 xdata E2uiOVRvol
445 _E2_ucDelayOV, //U8 xdata E2ucDelayOV
446 _E2_ucDelayOVR, //U8 xdata E2ucDelayOVR
447 _E2_uiChgEndVol,
448 _E2_siChgEndCurr,
449 _E2_ucChgEndDelay,
450 _E2_slOCCvol, //S32 xdata E2slOCCvol
451 _E2_ucDelayOCC, //U8 xdata E2ucDelayOCC
452 _E2_ucDelayOCCR, //U8 xdata E2ucDelayOCCR
453 _E2_ucRamCheckFlg2, //U8 xdata E2ucRamCheckFlg2
454
455 //<2F>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x03 langth=21
456 _E2_uiUVvol, //U16 xdata E2uiUVvol
457 _E2_uiUVRvol, //U16 xdata E2uiUVRvol
458 _E2_ucDelayUV, //U8 xdata E2ucDelayUV
459 _E2_ucDelayUVR, //U8 xdata E2ucDelayUVR
460 _E2_uiDsgEndVol,
461 _E2_ucDsgEndDelay,
462 _E2_uiOCDvol, //S32 xdata E2uiOCDvol
463 _E2_ucDelayOCD, //U8 xdata E2ucDelayOCD
464 _E2_slOCD2vol, //S32 xdata E2slOCD2vol
465 _E2_ucDelayOCD2, //U8 xdata E2ucDelayOCD2
466 _E2_ucDelayLoadR, //U8 xdata E2ucDelayLoadR
467 _E2_ucRamCheckFlg3, //U8 xdata E2ucRamCheckFlg3
468
469
470 //<2F>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x05 langth=5
471 _E2_DSG1PWMFreq, //U16 xdata DSG1PWMFreq
472 _E2_DSG1PWMRatioL, //U8 xdata DSG1PWMRatioL
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473 _E2_DSG1PWMRatioH, //U8 xdata DSG1PWMRatioH
474 _E2_ucRamCheckFlg5, //U8 xdata E2ucRamCheckFlg5
475
476 //<2F><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x06 langth=11
477 _E2_TempOTC, //U16 xdata TempOTC
478 _E2_TempOTCR, //U16 xdata TempOTCR
479 _E2_TempUTC, //U16 xdata TempUTC
480 _E2_TempUTCR, //U16 xdata TempUTCR
481 _E2_DelayOTC, //U8 xdata DelayOTC
482 _E2_DelayOTCR, //U8 xdata DelayOTCR
483 _E2_ucRamCheckFlg6, //U8 xdata E2ucRamCheckFlg6
484
485 //<2F>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x07 langth=9
486 _E2_TempOTD, //U16 xdata TempOTD
487 _E2_TempOTDR, //U16 xdata TempOTDR
488 _E2_TempUTD, //U16 xdata TempUTD
489 _E2_TempUTDR, //U16 xdata TempUTDR
490 _E2_ucRamCheckFlg7, //U8 xdata E2ucRamCheckFlg7
491
492 //ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x08 langth=8
493 _E2_BalanceVol, // U16 xdata BalanceVol
494 _E2_BalanceVolDiff, // U16 xdata BalanceVolDiff
495 _E2_BalCurrent, // S16 xdata BalCurrent
496 _E2_BalanceDelay, // U8 xdata BalanceDelay
497 _E2_ucRamCheckFlg8, // U8 xdata E2ucRamCheckFlg8
498
499 //<2F><><EFBFBD><EFBFBD>ͳ<EFBFBD><CDB3> SubClassID=0x09 langth=17
500
501 _E2_ucSOC, //U8 xdata E2ucSOC
502
503 _E2_ulDfRC, //U32 xdata E2ulLastFCC
504
505 _E2_slDsgEndCurr, //U32 xdata E2slDsgEndCurr
506 _E2_ulCycleThresholdCount, //U32 xdata E2ulCycleThresholdCount
507 _E2_uiLastCCount,
508 _E2_ucDsgEndFlg, //U8 xdata E2ucDsgEndFlg
509 _E2_ucRamCheckFlg9, //U8 xdata E2ucRamCheckFlg9
510
511 //AFE<46><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0A langth=4
512 _E2_AFEProtectConfig, // U8 xdata AFEProtectConfig
513 _E2_AFEOVvol, // U16 xdata AFEOVvol
514 _E2_ucRamCheckFlgA, // U8 xdata E2ucRamCheckFlgA
515
516 //У׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0B langth=12
517 _E2_uiVPackGain, //U16 xdata E2uiVPackGain
518 _E2_siCadcGain, //S16 xdata E2siCadcGain
519 _E2_siCadcOffset, //S16 xdata E2siCadcOffset
520 _E2_siTS0Offset, //S16 xdata E2siTS0Offset
521 _E2_siTS1Offset, //S16 xdata E2siTS1Offset
522 _E2_ucCalibrated, //S16 xdata E2ucCalibrated
523 _E2_ucRamCheckFlgB, //U8 xdata E2ucRamCheckFlgB
524 },
525
526 _FLASH_CHECK_DATA, // U16 xdata FlashCheck
527 /*********************************************************************************************************
-********/
528 //<2F><><EFBFBD><EFBFBD>B<EFBFBD><42>
529 /*********************************************************************************************************
-********/
530 /*********************************************************************************************************
-********/
531 //ϵͳ<CFB5><CDB3>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>ʼ SubClassID=0x00 langth=48
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532 {
533 _E2_PACKCONFIGMAP, //U16 xdata E2uiPackConfigMap
534 _E2_VOC10, //U16 xdata VOC10
535 _E2_VOC20, //U16 xdata VOC20
536 _E2_VOC30, //U16 xdata VOC30
537 _E2_VOC40, //U16 xdata VOC40
538 _E2_VOC50, //U16 xdata VOC50
539 _E2_VOC60, //U16 xdata VOC60
540 _E2_VOC70, //U16 xdata VOC70
541 _E2_VOC80, //U16 xdata VOC80
542 _E2_VOC90, //U16 xdata VOC90
543 _E2_VOC100, //U16 xdata VOC100
544 _E2_ulDesignCapacity, // U32 xdata E2ulDesignCapacity
545 _E2_ulFCC, // U32 xdata E2ulFCC
546 _E2_ulCycleThreshold, // U32 xdata E2uiCycleThreshold
547 _E2_uiCycleCount, // U16 xdata E2uiCycleCount
548 _E2_uiLearnLowTempe, // U16 xdata E2uiLearnLowTempe
549 _E2_Reserve, // U16 xdata E2Reserve
550 _E2_siDfilterCur, // S16 xdata E2siDfilterCur
551 _E2_ucLowPowerDeley, // U8 xdata E2ucLowPowerDeley
552 _E2_ucChgBKDelay, // U8 xdata E2ucChgBKDelay
553 _E2_siChgBKCur, // S16 xdata E2siChgBKCur
554 _E2_ucRTCBKDelay, // U8 xdata E2ucRTCBKDelay
555 _E2_ucRamCheckFlg0, // U8 xdata E2ucRamCheckFlg0
556
557
558 //<2F>û<EFBFBD><C3BB>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x01 length=50
559 _E2_SWVersion, //U16 xdata SWVersion
560 _E2_HWVersion, //U16 xdata HWVersion
561 _E2_ID, //U8 xdata ID
562 _E2_MNFName, //U8 xdata MNFName[12]
563 _E2_MNFDate, //U32 xdata MNFDate
564 _E2_SerialNum, //U16 xdata SerialNum
565 _E2_DeviceName, //U8 xdata DeviceName[12]
566 _E2_DeviceChem, //U8 xdata DeviceChem[12]
567 _E2_ChemID, //U16 xdata ChemID
568 _E2_ucRamCheckFlg1, //U8 xdata E2ucRamCheckFlg1
569
570 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x02 length=18
571 _E2_uiOVvol, //U16 xdata E2uiOVvol
572 _E2_uiOVRvol, //U16 xdata E2uiOVRvol
573 _E2_ucDelayOV, //U8 xdata E2ucDelayOV
574 _E2_ucDelayOVR, //U8 xdata E2ucDelayOVR
575 _E2_uiChgEndVol,
576 _E2_siChgEndCurr,
577 _E2_ucChgEndDelay,
578 _E2_slOCCvol, //S32 xdata E2slOCCvol
579 _E2_ucDelayOCC, //U8 xdata E2ucDelayOCC
580 _E2_ucDelayOCCR, //U8 xdata E2ucDelayOCCR
581 _E2_ucRamCheckFlg2, //U8 xdata E2ucRamCheckFlg2
582
583 //<2F>ŵ<EFBFBD><C5B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x03 langth=21
584 _E2_uiUVvol, //U16 xdata E2uiUVvol
585 _E2_uiUVRvol, //U16 xdata E2uiUVRvol
586 _E2_ucDelayUV, //U8 xdata E2ucDelayUV
587 _E2_ucDelayUVR, //U8 xdata E2ucDelayUVR
588 _E2_uiDsgEndVol,
589 _E2_ucDsgEndDelay,
590 _E2_uiOCDvol, //S32 xdata E2uiOCDvol
591 _E2_ucDelayOCD, //U8 xdata E2ucDelayOCD
592 _E2_slOCD2vol, //S32 xdata E2slOCD2vol
593 _E2_ucDelayOCD2, //U8 xdata E2ucDelayOCD2
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594 _E2_ucDelayLoadR, //U8 xdata E2ucDelayLoadR
595 _E2_ucRamCheckFlg3, //U8 xdata E2ucRamCheckFlg3
596
597
598 //<2F>ŵ<EFBFBD>PWM<57><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x05 langth=5
599 _E2_DSG1PWMFreq, //U16 xdata DSG1PWMFreq
600 _E2_DSG1PWMRatioL, //U8 xdata DSG1PWMRatioL
601 _E2_DSG1PWMRatioH, //U8 xdata DSG1PWMRatioH
602 _E2_ucRamCheckFlg5, //U8 xdata E2ucRamCheckFlg5
603
604 //<2F><><EFBFBD><EFBFBD><EFBFBD>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x06 langth=11
605 _E2_TempOTC, //U16 xdata TempOTC
606 _E2_TempOTCR, //U16 xdata TempOTCR
607 _E2_TempUTC, //U16 xdata TempUTC
608 _E2_TempUTCR, //U16 xdata TempUTCR
609 _E2_DelayOTC, //U8 xdata DelayOTC
610 _E2_DelayOTCR, //U8 xdata DelayOTCR
611 _E2_ucRamCheckFlg6, //U8 xdata E2ucRamCheckFlg6
612
613 //<2F>ŵ<EFBFBD><C5B5>¶ȱ<C2B6><C8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x07 langth=9
614 _E2_TempOTD, //U16 xdata TempOTD
615 _E2_TempOTDR, //U16 xdata TempOTDR
616 _E2_TempUTD, //U16 xdata TempUTD
617 _E2_TempUTDR, //U16 xdata TempUTDR
618 _E2_ucRamCheckFlg7, //U8 xdata E2ucRamCheckFlg7
619
620 //ƽ<><C6BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x08 langth=8
621 _E2_BalanceVol, // U16 xdata BalanceVol
622 _E2_BalanceVolDiff, // U16 xdata BalanceVolDiff
623 _E2_BalCurrent, // S16 xdata BalCurrent
624 _E2_BalanceDelay, // U8 xdata BalanceDelay
625 _E2_ucRamCheckFlg8, // U8 xdata E2ucRamCheckFlg8
626
627 //<2F><><EFBFBD><EFBFBD>ͳ<EFBFBD><CDB3> SubClassID=0x09 langth=17
628 _E2_ucSOC, //U8 xdata E2ucSOC
629 _E2_ulDfRC, //U32 xdata E2ulLastFCC
630 _E2_slDsgEndCurr, //U32 xdata E2slDsgEndCurr
631 _E2_ulCycleThresholdCount, //U32 xdata E2ulCycleThresholdCount
632 _E2_uiLastCCount,
633 _E2_ucDsgEndFlg, //U8 xdata E2ucDsgEndFlg
634
635 _E2_ucRamCheckFlg9, //U8 xdata E2ucRamCheckFlg9
636
637 //AFE<46><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0A langth=4
638 _E2_AFEProtectConfig, // U8 xdata AFEProtectConfig
639 _E2_AFEOVvol, // U16 xdata AFEOVvol
640 _E2_ucRamCheckFlgA, // U8 xdata E2ucRamCheckFlgA
641
642 //У׼<D0A3><D7BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ SubClassID=0x0B langth=12
643 _E2_uiVPackGain, //U16 xdata E2uiVPackGain
644 _E2_siCadcGain, //S16 xdata E2siCadcGain
645 _E2_siCadcOffset, //S16 xdata E2siCadcOffset
646 _E2_siTS0Offset, //S16 xdata E2siTS0Offset
647 _E2_siTS1Offset, //S16 xdata E2siTS1Offset
648 _E2_ucCalibrated, //S16 xdata E2ucCalibrated
649 _E2_ucRamCheckFlgB, //U8 xdata E2ucRamCheckFlgB
650 },
651
652 _FLASH_CHECK_DATA, // U16 xdata FlashCheck
653 };
654
655 //*** <<< end of configuration section >>> ***
修改Flash默认电池串数
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First commit
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MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = ---- ----
CONSTANT SIZE = 1024 ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)