866 lines
35 KiB
C
866 lines
35 KiB
C
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/**
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******************************************************************************
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* @file stm32l4xx_ll_fmc.h
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* @author MCD Application Team
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* @brief Header file of FMC HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32L4xx_LL_FMC_H
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#define STM32L4xx_LL_FMC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l4xx_hal_def.h"
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/** @addtogroup STM32L4xx_HAL_Driver
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* @{
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*/
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/** @addtogroup FMC_LL
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* @{
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*/
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/** @addtogroup FMC_LL_Private_Macros
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* @{
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*/
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#if defined(FMC_BANK1)
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#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
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((__BANK__) == FMC_NORSRAM_BANK2) || \
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((__BANK__) == FMC_NORSRAM_BANK3) || \
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((__BANK__) == FMC_NORSRAM_BANK4))
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#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
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((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
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#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
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((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
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((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
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#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
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((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
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((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
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#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
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((__SIZE__) == FMC_PAGE_SIZE_128) || \
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((__SIZE__) == FMC_PAGE_SIZE_256) || \
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((__SIZE__) == FMC_PAGE_SIZE_512) || \
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((__SIZE__) == FMC_PAGE_SIZE_1024))
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#if defined(FMC_BCR1_WFDIS)
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#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
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((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
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#endif /* FMC_BCR1_WFDIS */
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#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
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((__MODE__) == FMC_ACCESS_MODE_B) || \
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((__MODE__) == FMC_ACCESS_MODE_C) || \
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((__MODE__) == FMC_ACCESS_MODE_D))
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#if defined(FMC_BCRx_NBLSET)
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#define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \
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((__NBL__) == FMC_NBL_SETUPTIME_1) || \
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((__NBL__) == FMC_NBL_SETUPTIME_2) || \
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((__NBL__) == FMC_NBL_SETUPTIME_3))
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#endif /* FMC_BCRx_NBLSET */
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#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
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((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
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#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
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((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
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#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
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((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
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#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
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((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
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#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
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((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
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#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
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((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
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#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
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((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
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#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
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#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
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((__BURST__) == FMC_WRITE_BURST_ENABLE))
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#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
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((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
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#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
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#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
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#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
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#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
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#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
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#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
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#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
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#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
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#if defined(FMC_PCSCNTR_CSCOUNT)
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#define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U))
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#endif /* FMC_PCSCNTR_CSCOUNT */
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#endif /* FMC_BANK1 */
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#if defined(FMC_BANK3)
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#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
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#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
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((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
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#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \
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((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
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#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
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((__STATE__) == FMC_NAND_ECC_ENABLE))
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#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
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((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
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((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
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((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
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((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
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((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
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#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
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#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
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#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
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#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
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#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
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#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
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#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
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#endif /* FMC_BANK3 */
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/**
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* @}
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*/
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/* Exported typedef ----------------------------------------------------------*/
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/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types
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* @{
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*/
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#if defined(FMC_BANK1)
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#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
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#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
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#endif /* FMC_BANK1 */
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#if defined(FMC_BANK3)
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#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
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#endif /* FMC_BANK3 */
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#if defined(FMC_BANK1)
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#define FMC_NORSRAM_DEVICE FMC_Bank1_R
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#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R
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#endif /* FMC_BANK1 */
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#if defined(FMC_BANK3)
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#define FMC_NAND_DEVICE FMC_Bank3_R
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#endif /* FMC_BANK3 */
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#if defined(FMC_BANK1)
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/**
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* @brief FMC NORSRAM Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
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This parameter can be a value of @ref FMC_NORSRAM_Bank */
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uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
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multiplexed on the data bus or not.
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This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
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uint32_t MemoryType; /*!< Specifies the type of external memory attached to
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the corresponding memory device.
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This parameter can be a value of @ref FMC_Memory_Type */
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uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
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This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
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uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
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valid only with synchronous burst Flash memories.
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This parameter can be a value of @ref FMC_Burst_Access_Mode */
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uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
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the Flash memory in burst mode.
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This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
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uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
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clock cycle before the wait state or during the wait state,
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valid only when accessing memories in burst mode.
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This parameter can be a value of @ref FMC_Wait_Timing */
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uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
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This parameter can be a value of @ref FMC_Write_Operation */
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uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
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signal, valid for Flash memory access in burst mode.
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This parameter can be a value of @ref FMC_Wait_Signal */
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uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
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This parameter can be a value of @ref FMC_Extended_Mode */
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uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
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valid only with asynchronous Flash memories.
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This parameter can be a value of @ref FMC_AsynchronousWait */
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uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
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This parameter can be a value of @ref FMC_Write_Burst */
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uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
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This parameter is only enabled through the FMC_BCR1 register,
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and don't care through FMC_BCR2..4 registers.
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This parameter can be a value of @ref FMC_Continous_Clock */
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uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
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This parameter is only enabled through the FMC_BCR1 register,
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and don't care through FMC_BCR2..4 registers.
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This parameter can be a value of @ref FMC_Write_FIFO */
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uint32_t PageSize; /*!< Specifies the memory page size.
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This parameter can be a value of @ref FMC_Page_Size */
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uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number
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This parameter can be a value of @ref FMC_Byte_Lane */
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#if defined(FMC_PCSCNTR_CSCOUNT)
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FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this
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NSBank for PSRAM refresh.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for
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synchronous accesses and in HCLK cycles for asynchronous accesses,
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valid only if MaxChipSelectPulse is ENABLE.
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This parameter can be a value between Min_Data = 1 and Max_Data = 65535.
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@note: This parameter is common to all NSBank. */
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#endif
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} FMC_NORSRAM_InitTypeDef;
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/**
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* @brief FMC NORSRAM Timing parameters structure definition
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*/
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typedef struct
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{
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uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the address setup time.
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This parameter can be a value between Min_Data = 0 and Max_Data = 15.
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@note This parameter is not used with synchronous NOR Flash memories. */
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uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the address hold time.
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This parameter can be a value between Min_Data = 1 and Max_Data = 15.
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@note This parameter is not used with synchronous NOR Flash memories. */
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uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the data setup time.
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This parameter can be a value between Min_Data = 1 and Max_Data = 255.
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@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
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NOR Flash memories. */
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uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure
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the duration of the data hold time.
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This parameter can be a value between Min_Data = 0 and Max_Data = 3.
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@note This parameter is used for used in asynchronous accesses. */
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uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
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the duration of the bus turnaround.
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This parameter can be a value between Min_Data = 0 and Max_Data = 15.
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@note This parameter is only used for multiplexed NOR Flash memories. */
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uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
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HCLK cycles. This parameter can be a value between Min_Data = 2 and
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Max_Data = 16.
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@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
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accesses. */
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uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
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to the memory before getting the first data.
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The parameter value depends on the memory type as shown below:
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- It must be set to 0 in case of a CRAM
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- It is don't care in asynchronous NOR, SRAM or ROM accesses
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- It may assume a value between Min_Data = 2 and Max_Data = 17
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in NOR Flash memories with synchronous burst mode enable */
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uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
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This parameter can be a value of @ref FMC_Access_Mode */
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} FMC_NORSRAM_TimingTypeDef;
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#endif /* FMC_BANK1 */
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#if defined(FMC_BANK3)
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/**
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* @brief FMC NAND Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
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This parameter can be a value of @ref FMC_NAND_Bank */
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uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
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This parameter can be any value of @ref FMC_Wait_feature */
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||
|
|
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
|
||
|
|
This parameter can be any value of @ref FMC_NAND_Data_Width */
|
||
|
|
|
||
|
|
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
|
||
|
|
This parameter can be any value of @ref FMC_ECC */
|
||
|
|
|
||
|
|
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
|
||
|
|
This parameter can be any value of @ref FMC_ECC_Page_Size */
|
||
|
|
|
||
|
|
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||
|
|
delay between CLE low and RE low.
|
||
|
|
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
|
||
|
|
|
||
|
|
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||
|
|
delay between ALE low and RE low.
|
||
|
|
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
|
||
|
|
} FMC_NAND_InitTypeDef;
|
||
|
|
#endif /* FMC_BANK3 */
|
||
|
|
|
||
|
|
#if defined(FMC_BANK3)
|
||
|
|
/**
|
||
|
|
* @brief FMC NAND Timing parameters structure definition
|
||
|
|
*/
|
||
|
|
typedef struct
|
||
|
|
{
|
||
|
|
uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
|
||
|
|
the command assertion for NAND-Flash read or write access
|
||
|
|
to common/Attribute or I/O memory space (depending on
|
||
|
|
the memory space timing to be configured).
|
||
|
|
This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
|
||
|
|
|
||
|
|
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
|
||
|
|
command for NAND-Flash read or write access to
|
||
|
|
common/Attribute or I/O memory space (depending on the
|
||
|
|
memory space timing to be configured).
|
||
|
|
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
|
||
|
|
|
||
|
|
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
|
||
|
|
(and data for write access) after the command de-assertion
|
||
|
|
for NAND-Flash read or write access to common/Attribute
|
||
|
|
or I/O memory space (depending on the memory space timing
|
||
|
|
to be configured).
|
||
|
|
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
|
||
|
|
|
||
|
|
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
|
||
|
|
data bus is kept in HiZ after the start of a NAND-Flash
|
||
|
|
write access to common/Attribute or I/O memory space (depending
|
||
|
|
on the memory space timing to be configured).
|
||
|
|
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
|
||
|
|
} FMC_NAND_PCC_TimingTypeDef;
|
||
|
|
#endif /* FMC_BANK3 */
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Exported constants --------------------------------------------------------*/
|
||
|
|
/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#if defined(FMC_BANK1)
|
||
|
|
|
||
|
|
/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_NORSRAM_BANK1 (0x00000000U)
|
||
|
|
#define FMC_NORSRAM_BANK2 (0x00000002U)
|
||
|
|
#define FMC_NORSRAM_BANK3 (0x00000004U)
|
||
|
|
#define FMC_NORSRAM_BANK4 (0x00000006U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
|
||
|
|
#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_Memory_Type FMC Memory Type
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_MEMORY_TYPE_SRAM (0x00000000U)
|
||
|
|
#define FMC_MEMORY_TYPE_PSRAM (0x00000004U)
|
||
|
|
#define FMC_MEMORY_TYPE_NOR (0x00000008U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
|
||
|
|
#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
|
||
|
|
#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
|
||
|
|
#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
|
||
|
|
#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
|
||
|
|
#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_Wait_Timing FMC Wait Timing
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
|
||
|
|
#define FMC_WAIT_TIMING_DURING_WS (0x00000800U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_Write_Operation FMC Write Operation
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_WRITE_OPERATION_DISABLE (0x00000000U)
|
||
|
|
#define FMC_WRITE_OPERATION_ENABLE (0x00001000U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_Wait_Signal FMC Wait Signal
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U)
|
||
|
|
#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_Extended_Mode FMC Extended Mode
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_EXTENDED_MODE_DISABLE (0x00000000U)
|
||
|
|
#define FMC_EXTENDED_MODE_ENABLE (0x00004000U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
|
||
|
|
#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_Page_Size FMC Page Size
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_PAGE_SIZE_NONE (0x00000000U)
|
||
|
|
#define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0
|
||
|
|
#define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1
|
||
|
|
#define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\
|
||
|
|
| FMC_BCRx_CPSIZE_1)
|
||
|
|
#define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_Write_Burst FMC Write Burst
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_WRITE_BURST_DISABLE (0x00000000U)
|
||
|
|
#define FMC_WRITE_BURST_ENABLE (0x00080000U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_Continous_Clock FMC Continuous Clock
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
|
||
|
|
#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#if defined(FMC_BCR1_WFDIS)
|
||
|
|
/** @defgroup FMC_Write_FIFO FMC Write FIFO
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS
|
||
|
|
#define FMC_WRITE_FIFO_ENABLE (0x00000000U)
|
||
|
|
#endif /* FMC_BCR1_WFDIS */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_Access_Mode FMC Access Mode
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_ACCESS_MODE_A (0x00000000U)
|
||
|
|
#define FMC_ACCESS_MODE_B (0x10000000U)
|
||
|
|
#define FMC_ACCESS_MODE_C (0x20000000U)
|
||
|
|
#define FMC_ACCESS_MODE_D (0x30000000U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_NBL_SETUPTIME_0 (0x00000000U)
|
||
|
|
#define FMC_NBL_SETUPTIME_1 (0x00400000U)
|
||
|
|
#define FMC_NBL_SETUPTIME_2 (0x00800000U)
|
||
|
|
#define FMC_NBL_SETUPTIME_3 (0x00C00000U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
#endif /* FMC_BANK1 */
|
||
|
|
|
||
|
|
#if defined(FMC_BANK3)
|
||
|
|
|
||
|
|
/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/** @defgroup FMC_NAND_Bank FMC NAND Bank
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_NAND_BANK3 (0x00000100U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_Wait_feature FMC Wait feature
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U)
|
||
|
|
#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U)
|
||
|
|
#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_ECC FMC ECC
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_NAND_ECC_DISABLE (0x00000000U)
|
||
|
|
#define FMC_NAND_ECC_ENABLE (0x00000040U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
|
||
|
|
#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
|
||
|
|
#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
|
||
|
|
#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
|
||
|
|
#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
|
||
|
|
#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
#endif /* FMC_BANK3 */
|
||
|
|
|
||
|
|
|
||
|
|
/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#if defined(FMC_BANK3)
|
||
|
|
#define FMC_IT_RISING_EDGE (0x00000008U)
|
||
|
|
#define FMC_IT_LEVEL (0x00000010U)
|
||
|
|
#define FMC_IT_FALLING_EDGE (0x00000020U)
|
||
|
|
#endif /* FMC_BANK3 */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#if defined(FMC_BANK3)
|
||
|
|
#define FMC_FLAG_RISING_EDGE (0x00000001U)
|
||
|
|
#define FMC_FLAG_LEVEL (0x00000002U)
|
||
|
|
#define FMC_FLAG_FALLING_EDGE (0x00000004U)
|
||
|
|
#define FMC_FLAG_FEMPT (0x00000040U)
|
||
|
|
#endif /* FMC_BANK3 */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Private macro -------------------------------------------------------------*/
|
||
|
|
/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#if defined(FMC_BANK1)
|
||
|
|
/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
|
||
|
|
* @brief macros to handle NOR device enable/disable and read/write operations
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable the NORSRAM device access.
|
||
|
|
* @param __INSTANCE__ FMC_NORSRAM Instance
|
||
|
|
* @param __BANK__ FMC_NORSRAM Bank
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
|
||
|
|
|= FMC_BCRx_MBKEN)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable the NORSRAM device access.
|
||
|
|
* @param __INSTANCE__ FMC_NORSRAM Instance
|
||
|
|
* @param __BANK__ FMC_NORSRAM Bank
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
|
||
|
|
&= ~FMC_BCRx_MBKEN)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
#endif /* FMC_BANK1 */
|
||
|
|
|
||
|
|
#if defined(FMC_BANK3)
|
||
|
|
/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
|
||
|
|
* @brief macros to handle NAND device enable/disable
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable the NAND device access.
|
||
|
|
* @param __INSTANCE__ FMC_NAND Instance
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable the NAND device access.
|
||
|
|
* @param __INSTANCE__ FMC_NAND Instance
|
||
|
|
* @param __BANK__ FMC_NAND Bank
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
#endif /* FMC_BANK3 */
|
||
|
|
|
||
|
|
#if defined(FMC_BANK3)
|
||
|
|
/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt
|
||
|
|
* @brief macros to handle NAND interrupts
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable the NAND device interrupt.
|
||
|
|
* @param __INSTANCE__ FMC_NAND instance
|
||
|
|
* @param __INTERRUPT__ FMC_NAND interrupt
|
||
|
|
* This parameter can be any combination of the following values:
|
||
|
|
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
|
||
|
|
* @arg FMC_IT_LEVEL: Interrupt level.
|
||
|
|
* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable the NAND device interrupt.
|
||
|
|
* @param __INSTANCE__ FMC_NAND Instance
|
||
|
|
* @param __INTERRUPT__ FMC_NAND interrupt
|
||
|
|
* This parameter can be any combination of the following values:
|
||
|
|
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
|
||
|
|
* @arg FMC_IT_LEVEL: Interrupt level.
|
||
|
|
* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Get flag status of the NAND device.
|
||
|
|
* @param __INSTANCE__ FMC_NAND Instance
|
||
|
|
* @param __BANK__ FMC_NAND Bank
|
||
|
|
* @param __FLAG__ FMC_NAND flag
|
||
|
|
* This parameter can be any combination of the following values:
|
||
|
|
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
||
|
|
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
|
||
|
|
* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
||
|
|
* @arg FMC_FLAG_FEMPT: FIFO empty flag.
|
||
|
|
* @retval The state of FLAG (SET or RESET).
|
||
|
|
*/
|
||
|
|
#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Clear flag status of the NAND device.
|
||
|
|
* @param __INSTANCE__ FMC_NAND Instance
|
||
|
|
* @param __FLAG__ FMC_NAND flag
|
||
|
|
* This parameter can be any combination of the following values:
|
||
|
|
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
|
||
|
|
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
|
||
|
|
* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
|
||
|
|
* @arg FMC_FLAG_FEMPT: FIFO empty flag.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
#endif /* FMC_BANK3 */
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Private functions ---------------------------------------------------------*/
|
||
|
|
/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
#if defined(FMC_BANK1)
|
||
|
|
/** @defgroup FMC_LL_NORSRAM NOR SRAM
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
|
||
|
|
FMC_NORSRAM_InitTypeDef *Init);
|
||
|
|
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
|
||
|
|
FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
|
||
|
|
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
|
||
|
|
FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
|
||
|
|
uint32_t ExtendedMode);
|
||
|
|
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
|
||
|
|
FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
|
||
|
|
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
#endif /* FMC_BANK1 */
|
||
|
|
|
||
|
|
#if defined(FMC_BANK3)
|
||
|
|
/** @defgroup FMC_LL_NAND NAND
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
|
||
|
|
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
|
||
|
|
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
||
|
|
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
|
||
|
|
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
|
||
|
|
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
|
||
|
|
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
|
||
|
|
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
|
||
|
|
uint32_t Timeout);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
#endif /* FMC_BANK3 */
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* STM32L4xx_LL_FMC_H */
|