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在错误中断里添加了重启，ADC转换周期改为6.5

This commit is contained in:
95384 2024-09-21 11:35:13 +08:00
parent ddd4b155b9
commit 01442fde3d
151 changed files with 53978 additions and 53970 deletions
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3
App/Src/anemometer_dev.c
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@ -183,7 +183,8 @@ float32_t cal_tof(q15_t* x,uint32_t len)
//echo_dt = (x[i-1]-x[i+1])/2.0/(x[i-1]-2*x[i]+x[i+1]);
echo_dt = find_maxValPosition_by_sinInterpolation(x[i-1],x[i],x[i+1]);
echo_p = (float32_t)i+echo_dt-0*(float32_t)(ADC_SAMP_RATE_MHz/DRIVE_FREQ_MHz);
return echo_p;
}
// 如果15% ~45%之间的数据未找到，则找45-80%的顶点。

2
Core/Src/adc.c
View File

@ -76,7 +76,7 @@ void MX_ADC1_Init(void)
*/
sConfig.Channel = ADC_CHANNEL_1;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_12CYCLES_5;
sConfig.SamplingTime = ADC_SAMPLETIME_6CYCLES_5;
sConfig.SingleDiff = ADC_SINGLE_ENDED;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;

3
Core/Src/stm32l4xx_it.c
View File

@ -95,7 +95,8 @@ void NMI_Handler(void)
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
__iar_builtin_set_FAULTMASK(1);
NVIC_SystemReset();
/* USER CODE END HardFault_IRQn 0 */
while (1)
{

2
EWARM/micro_climate.ewp
View File

@ -676,7 +676,7 @@
<option>
<name>OOCOutputFormat</name>
<version>3</version>
<state>1</state>
<state>3</state>
</option>
<option>
<name>OCOutputOverride</name>

978
EWARM/micro_climate/.micro_climate_build_cache
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File diff suppressed because it is too large Load Diff

BIN
EWARM/micro_climate/.ninja_deps
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Binary file not shown.

212
EWARM/micro_climate/.ninja_log
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@ -1,141 +1,73 @@
# ninja log v5
213 647 7466029099148074 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/dma.o bf43722906c03566
1757 2354 7466029115911120 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_dma.o 91d866fecc8c1f1a
151 591 7466029098570755 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/gpio.o 5d9d7bd8f6ba44c0
1277 1427 7466029107043242 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/RingQueue_10900368326811202236.dir/ring_queue.o f0be3f60b5bfc513
3253 5457 7466029147240607 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_tim.o bb0cd7722c4f38a4
725 1193 7466029104351540 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/stm32l4xx_hal_timebase_tim.o f1bce46cd257c176
516 998 7466029102697954 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/i2c.o c1fb605878ec3f5b
648 1276 7466029104451559 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/spi.o a8bea0bf06ab2afe
785 997 7467033472597915 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/FreeRTOS_4809373609813369194.dir/croutine.o fec8dff9e3001349
337 810 7477486135747377 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/freertos.o dbcb0db307adc272
1246 1668 7466029109103457 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/CMSIS_6603591812247902717.dir/system_stm32l4xx.o 8af0a0bb5f37c063
392 1056 7477486138102502 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/EC801E_17758034221153603070.dir/EC801E.o a54b6de52d607a4f
4798 4935 7466029142170934 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/EWARM_18443280873093131863.dir/startup_stm32l496xx.o 983b34495e4a9f06
958 1371 7467033476277907 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/FreeRTOS_4809373609813369194.dir/stream_buffer.o a2c4202a3c04b26c
1164 1467 7466029107433245 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Filter_2427836196881467961.dir/filter.o 1021703d4dd9edaf
731 921 7467033471822693 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/FreeRTOS_4809373609813369194.dir/timers.o aec0756d465e7d4f
175 1467 7476326879215816 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/main.o a6886d12c2e968a7
806 1162 7466029104331544 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/stm32l4xx_hal_msp.o e5ab62ce53061ad9
1671 1901 7466029111788946 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Shell_738121877093898511.dir/shell_cmdhelp.o b3251e875919362e
2193 2602 7466029118727572 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_dma_ex.o e6241ebc22880fa8
925 1700 7467033479597963 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/FreeRTOS_4809373609813369194.dir/tasks.o 925e9e5e1f9c00b6
775 1244 7466029104461560 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/stm32l4xx_it.o d3b9c956d118e1e0
1219 1770 7467033480287952 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/FreeRTOS_4809373609813369194.dir/queue.o 32948f85b195dca
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1195 1755 7466029109925346 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/usart.o e0a5563efe00cc8
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2928 3735 7466029130054144 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_rcc.o cfc99b805f06fd21
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3186 3534 7466029127768885 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_spi_ex.o 474177df1723cbf
1719 2147 7466029114154233 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Shell_738121877093898511.dir/shell_uart.o 8b75033f8b86554
62 680 7466029098691186 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/adc.o 7fd39f29b6b2108a
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1951 2459 7466029117296284 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal.o 28d0611f7960d3c5
2605 3183 7466029124518157 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_exti.o 5230b767faebd3c7
1352 2259 7466029115290630 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Shell_738121877093898511.dir/shell.o fe96fc4cfc22cc63
1859 2305 7466029115480626 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_cortex.o ffd5c9fe60b1cb86
1187 1510 7467033477707954 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/FreeRTOS_4809373609813369194.dir/event_groups.o 2605e327da29e9c1
1905 2894 7466029121282834 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_adc_ex.o 37f4eb03dbc09aaa
3656 5161 7466029144321176 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_spi.o f38fe7acc918d43b
32 722 7466029099263223 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Src_5571640358672592439.dir/uart_dev.o a0d36a68c77f5f1a
2853 3318 7466029125873759 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_flash.o b4beadf6e004d839
2308 2683 7466029119522663 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_flash_ramfunc.o d260c0cb338f75bb
2462 3097 7466029123663058 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_pwr.o 2db3b7171b5c7eec
839 1350 7467033475227907 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/FreeRTOS_4809373609813369194.dir/heap_4.o 9cbc680675f46c5a
1799 3000 7466029122647957 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_adc.o caeb41ce376d6e07
2262 2850 7466029121172829 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_flash_ex.o c9b9b10c9c58c02f
2357 2926 7466029121362832 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_i2c_ex.o 62e9b3a1150d3a17
2896 3501 7466029127698885 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_pwr_ex.o 30bd4b15d276c369
3537 4051 7466029133229502 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_uart_ex.o 5cb6faeee735a211
2685 3250 7466029125163263 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_gpio.o 2d1e548c51a93c9
3504 4466 7466029137335399 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_rcc_ex.o e19c1f22ef08f9c4
691 1262 7467033474517908 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/FreeRTOS_4809373609813369194.dir/cmsis_os.o be977a9f349ad14c
1264 1385 7467033476527910 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/FreeRTOS_4809373609813369194.dir/portasm.o 97d4445452c7ac15
2150 4349 7466029136160299 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_i2c.o a8caa8580e5e5d8b
3003 4184 7466029134484625 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_tim_ex.o 81aff70c2ae41a09
3320 4690 7466029139595621 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_uart.o 1a77cf0adff1965
1000 1217 7467033474457921 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/FreeRTOS_4809373609813369194.dir/port.o a4849925602de71e
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32 1031 7467033471832711 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Src_5571640358672592439.dir/anemometer_dev.o 3ee494bfbe2660af
1033 1183 7467033474457921 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/FreeRTOS_4809373609813369194.dir/list.o cbbfd62742ca92f9
1058 1964 7477486147292293 E:/Y/IAR/micro_climate/EWARM/micro_climate/Exe/micro_climate.out 42c24b588bc0dc40
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61 1606 7467033478657960 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/cJSON.o d89cf30001a6f46f
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622 862 7484989353947694 E:/Y/IAR/micro_climate/EWARM/micro_climate/Exe/micro_climate.out 42c24b588bc0dc40
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32 449 7484989425439866 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/dma.o bf43722906c03566
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116 578 7484989426317343 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/spi.o a8bea0bf06ab2afe
172 622 7484989426783696 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/stm32l4xx_hal_msp.o e5ab62ce53061ad9
143 655 7484989426793698 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/i2c.o c1fb605878ec3f5b
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657 825 7484989429240482 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Filter_2427836196881467961.dir/filter.o 1021703d4dd9edaf
451 970 7484989430647474 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/stm32l4xx_it.o d3b9c956d118e1e0
538 1009 7484989430722542 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/stm32l4xx_hal_timebase_tim.o f1bce46cd257c176
625 1049 7484989431102877 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/CMSIS_6603591812247902717.dir/system_stm32l4xx.o 8af0a0bb5f37c063
581 1098 7484989431905155 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Core_13247989168731456611.dir/usart.o e0a5563efe00cc8
972 1139 7484989432386162 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/RingQueue_10900368326811202236.dir/ring_queue.o f0be3f60b5bfc513
783 1296 7484989433903316 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/HP203B_1856951872026386537.dir/hp203b.o c3cee707e37d4a42
1141 1337 7484989434371108 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/Shell_738121877093898511.dir/shell_cmdhist.o 38590687c47a2cbc
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1718 2099 7484989441658363 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_i2c_ex.o 62e9b3a1150d3a17
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1880 2375 7484989444669925 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_exti.o 5230b767faebd3c7
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2204 2610 7484989447020679 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_dma_ex.o e6241ebc22880fa8
1574 2657 7484989447190678 E:/Y/IAR/micro_climate/EWARM/micro_climate/Obj/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_adc_ex.o 37f4eb03dbc09aaa
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E:\Y\IAR\micro_climate\EWARM\..\Drivers\CMSIS\Include\core_cm4.h \
E:\Y\IAR\micro_climate\EWARM\..\Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l496xx.h \
E:\Y\IAR\micro_climate\EWARM\..\Drivers\CMSIS\Device\ST\STM32L4xx\Include\stm32l4xx.h \
E:\Y\IAR\micro_climate\EWARM\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_def.h \
E:\Y\IAR\micro_climate\EWARM\..\Drivers\STM32L4xx_HAL_Driver\Inc\stm32l4xx_hal_rcc.h \
E:\Y\IAR\micro_climate\EWARM\..\Core\Inc\stm32l4xx_hal_conf.h \
E:\Y\IAR\micro_climate\EWARM\..\Core\Inc\main.h \
E:\Y\IAR\micro_climate\EWARM\..\Core\Inc\usart.h \
D:\Program\ Files\IAR\ Systems\arm\inc\c\DLib_Product_string.h \
D:\Program\ Files\IAR\ Systems\arm\inc\c\ysizet.h \
D:\Program\ Files\IAR\ Systems\arm\inc\c\DLib_Product.h \
D:\Program\ Files\IAR\ Systems\arm\inc\c\DLib_Config_Normal.h \
D:\Program\ Files\IAR\ Systems\arm\inc\c\DLib_Defaults.h \
D:\Program\ Files\IAR\ Systems\arm\inc\c\yvals.h \
D:\Program\ Files\IAR\ Systems\arm\inc\c\string.h \
E:\Y\IAR\micro_climate\EWARM\..\App\Inc\comm_types.h \
E:\Y\IAR\micro_climate\EWARM\..\Drivers\RingQueue\ring_queue.h \
E:\Y\IAR\micro_climate\EWARM\..\App\Inc\frt_protocol.h \
E:\Y\IAR\micro_climate\App\Src\frt_protocol.c

BIN
EWARM/micro_climate/BrowseInfo/micro_climate.pbd
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EWARM/micro_climate/BrowseInfo/micro_climate.pbd.browse
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EWARM/micro_climate/BrowseInfo/micro_climate.pbw
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EWARM/micro_climate/BrowseInfo/micro_climate_part0.pbi
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EWARM/micro_climate/BrowseInfo/micro_climate_part1.pbi
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EWARM/micro_climate/Exe/micro_climate.hex
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EWARM/micro_climate/Exe/micro_climate.out
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2
EWARM/micro_climate/List/CMSIS_6603591812247902717.dir/system_stm32l4xx.lst
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@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/CMSIS_6603591812247902717.dir/system_stm32l4xx.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/adc.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:06
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:52
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/adc.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:06
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:52
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/cJSON.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/cJSON.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/dma.lst
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@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:02
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:52
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/dma.s
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@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:02
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:52
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/freertos.lst
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@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:54:35
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:52
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/freertos.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:54:35
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:52
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/gpio.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:06
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:52
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/gpio.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:06
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:52
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/i2c.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:02
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/i2c.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:02
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

12
EWARM/micro_climate/List/Core_13247989168731456611.dir/main.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:02
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb
@ -505,19 +505,19 @@ E:\Y\IAR\micro_climate\Core\Src\main.c
\ In section .text, align 4, keep-with-next
\ ?_2:
\ 0x0 0x53 0x65 DC8 "Sep 20 2024"
\ 0x0 0x53 0x65 DC8 "Sep 21 2024"
\ 0x70 0x20
\ 0x32 0x30
\ 0x32 0x31
\ 0x20 0x32
\ 0x30 0x32
\ 0x34 0x00
\ In section .text, align 4, keep-with-next
\ ?_3:
\ 0x0 0x30 0x39 DC8 "09:29:02"
\ 0x0 0x31 0x31 DC8 "11:22:52"
\ 0x3A 0x32
\ 0x39 0x3A
\ 0x30 0x32
\ 0x32 0x3A
\ 0x35 0x32
\ 0x00
\ 0x9 DS8 3
257

6
EWARM/micro_climate/List/Core_13247989168731456611.dir/main.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:02
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb
@ -655,14 +655,14 @@ Error_Handler:
DATA
?_2:
DATA8
DC8 "Sep 20 2024"
DC8 "Sep 21 2024"
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
?_3:
DATA8
DC8 "09:29:02"
DC8 "11:22:52"
DATA
DS8 3

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/spi.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:02
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:52
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/spi.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:02
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:52
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/stm32l4xx_hal_msp.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:02
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/stm32l4xx_hal_msp.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:02
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/stm32l4xx_hal_timebase_tim.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/stm32l4xx_hal_timebase_tim.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

508
EWARM/micro_climate/List/Core_13247989168731456611.dir/stm32l4xx_it.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:26:24
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb
@ -163,194 +163,208 @@ E:\Y\IAR\micro_climate\Core\Src\stm32l4xx_it.c
95 void HardFault_Handler(void)
96 {
97 /* USER CODE BEGIN HardFault_IRQn 0 */
98
99 /* USER CODE END HardFault_IRQn 0 */
100 while (1)
98 __iar_builtin_set_FAULTMASK(1);
\ HardFault_Handler: (+1)
\ 0x0 0x2001 MOVS R0,#+1
\ 0x2 0xF380 0x8813 MSR FAULTMASK,R0
99 NVIC_SystemReset();
\ 0x6 0xF3BF 0x8F4F DSB SY
\ 0xA 0x.... LDR.N R1,??DataTable8
\ 0xC 0x.... LDR.N R0,??DataTable8_1
\ 0xE 0x680A LDR R2,[R1, #+0]
\ 0x10 0xF402 0x62E0 AND R2,R2,#0x700
\ 0x14 0x4302 ORRS R2,R0,R2
\ 0x16 0x600A STR R2,[R1, #+0]
\ 0x18 0xF3BF 0x8F4F DSB SY
\ ??HardFault_Handler_0: (+1)
\ 0x0 0xE7FE B.N ??HardFault_Handler_0
101 {
102 /* USER CODE BEGIN W1_HardFault_IRQn 0 */
103 /* USER CODE END W1_HardFault_IRQn 0 */
104 }
105 }
106
107 /**
108 * @brief This function handles Memory management fault.
109 */
\ 0x1C 0xBF00 Nop
\ 0x1E 0xE7FD B.N ??HardFault_Handler_0
100 /* USER CODE END HardFault_IRQn 0 */
101 while (1)
^
Warning[Pe128]: loop is not reachable
102 {
103 /* USER CODE BEGIN W1_HardFault_IRQn 0 */
104 /* USER CODE END W1_HardFault_IRQn 0 */
105 }
106 }
107
108 /**
109 * @brief This function handles Memory management fault.
110 */
\ In section .text, align 2, keep-with-next
110 void MemManage_Handler(void)
111 {
112 /* USER CODE BEGIN MemoryManagement_IRQn 0 */
113
114 /* USER CODE END MemoryManagement_IRQn 0 */
115 while (1)
111 void MemManage_Handler(void)
112 {
113 /* USER CODE BEGIN MemoryManagement_IRQn 0 */
114
115 /* USER CODE END MemoryManagement_IRQn 0 */
116 while (1)
\ MemManage_Handler: (+1)
\ ??MemManage_Handler_0: (+1)
\ 0x0 0xE7FE B.N ??MemManage_Handler_0
116 {
117 /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
118 /* USER CODE END W1_MemoryManagement_IRQn 0 */
119 }
120 }
121
122 /**
123 * @brief This function handles Prefetch fault, memory access fault.
124 */
117 {
118 /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
119 /* USER CODE END W1_MemoryManagement_IRQn 0 */
120 }
121 }
122
123 /**
124 * @brief This function handles Prefetch fault, memory access fault.
125 */
\ In section .text, align 2, keep-with-next
125 void BusFault_Handler(void)
126 {
127 /* USER CODE BEGIN BusFault_IRQn 0 */
128
129 /* USER CODE END BusFault_IRQn 0 */
130 while (1)
126 void BusFault_Handler(void)
127 {
128 /* USER CODE BEGIN BusFault_IRQn 0 */
129
130 /* USER CODE END BusFault_IRQn 0 */
131 while (1)
\ BusFault_Handler: (+1)
\ ??BusFault_Handler_0: (+1)
\ 0x0 0xE7FE B.N ??BusFault_Handler_0
131 {
132 /* USER CODE BEGIN W1_BusFault_IRQn 0 */
133 /* USER CODE END W1_BusFault_IRQn 0 */
134 }
135 }
136
137 /**
138 * @brief This function handles Undefined instruction or illegal state.
139 */
132 {
133 /* USER CODE BEGIN W1_BusFault_IRQn 0 */
134 /* USER CODE END W1_BusFault_IRQn 0 */
135 }
136 }
137
138 /**
139 * @brief This function handles Undefined instruction or illegal state.
140 */
\ In section .text, align 2, keep-with-next
140 void UsageFault_Handler(void)
141 {
142 /* USER CODE BEGIN UsageFault_IRQn 0 */
143
144 /* USER CODE END UsageFault_IRQn 0 */
145 while (1)
141 void UsageFault_Handler(void)
142 {
143 /* USER CODE BEGIN UsageFault_IRQn 0 */
144
145 /* USER CODE END UsageFault_IRQn 0 */
146 while (1)
\ UsageFault_Handler: (+1)
\ ??UsageFault_Handler_0: (+1)
\ 0x0 0xE7FE B.N ??UsageFault_Handler_0
146 {
147 /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
148 /* USER CODE END W1_UsageFault_IRQn 0 */
149 }
150 }
151
152 /**
153 * @brief This function handles Debug monitor.
154 */
147 {
148 /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
149 /* USER CODE END W1_UsageFault_IRQn 0 */
150 }
151 }
152
153 /**
154 * @brief This function handles Debug monitor.
155 */
\ In section .text, align 2, keep-with-next
155 void DebugMon_Handler(void)
156 {
157 /* USER CODE BEGIN DebugMonitor_IRQn 0 */
158
159 /* USER CODE END DebugMonitor_IRQn 0 */
160 /* USER CODE BEGIN DebugMonitor_IRQn 1 */
161
162 /* USER CODE END DebugMonitor_IRQn 1 */
163 }
156 void DebugMon_Handler(void)
157 {
158 /* USER CODE BEGIN DebugMonitor_IRQn 0 */
159
160 /* USER CODE END DebugMonitor_IRQn 0 */
161 /* USER CODE BEGIN DebugMonitor_IRQn 1 */
162
163 /* USER CODE END DebugMonitor_IRQn 1 */
164 }
\ DebugMon_Handler: (+1)
\ 0x0 0x4770 BX LR
164
165 /******************************************************************************/
166 /* STM32L4xx Peripheral Interrupt Handlers */
167 /* Add here the Interrupt Handlers for the used peripherals. */
168 /* For the available peripheral interrupt handler names, */
169 /* please refer to the startup file (startup_stm32l4xx.s). */
170 /******************************************************************************/
171
172 /**
173 * @brief This function handles DMA1 channel1 global interrupt.
174 */
165
166 /******************************************************************************/
167 /* STM32L4xx Peripheral Interrupt Handlers */
168 /* Add here the Interrupt Handlers for the used peripherals. */
169 /* For the available peripheral interrupt handler names, */
170 /* please refer to the startup file (startup_stm32l4xx.s). */
171 /******************************************************************************/
172
173 /**
174 * @brief This function handles DMA1 channel1 global interrupt.
175 */
\ In section .text, align 2, keep-with-next
175 void DMA1_Channel1_IRQHandler(void)
176 {
177 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
178
179 /* USER CODE END DMA1_Channel1_IRQn 0 */
180 HAL_DMA_IRQHandler(&hdma_adc1);
176 void DMA1_Channel1_IRQHandler(void)
177 {
178 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
179
180 /* USER CODE END DMA1_Channel1_IRQn 0 */
181 HAL_DMA_IRQHandler(&hdma_adc1);
\ DMA1_Channel1_IRQHandler: (+1)
\ 0x0 0x.... LDR.N R0,??DataTable7
\ 0x0 0x.... LDR.N R0,??DataTable8_2
\ 0x2 0x.... 0x.... B.W HAL_DMA_IRQHandler
181 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
182
183 /* USER CODE END DMA1_Channel1_IRQn 1 */
184 }
185
186 /**
187 * @brief This function handles TIM1 update interrupt and TIM16 global interrupt.
188 */
182 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
183
184 /* USER CODE END DMA1_Channel1_IRQn 1 */
185 }
186
187 /**
188 * @brief This function handles TIM1 update interrupt and TIM16 global interrupt.
189 */
\ In section .text, align 2, keep-with-next
189 void TIM1_UP_TIM16_IRQHandler(void)
190 {
190 void TIM1_UP_TIM16_IRQHandler(void)
191 {
\ TIM1_UP_TIM16_IRQHandler: (+1)
\ 0x0 0xB580 PUSH {R7,LR}
191 /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */
192
193 /* USER CODE END TIM1_UP_TIM16_IRQn 0 */
194 HAL_TIM_IRQHandler(&htim1);
\ 0x2 0x.... LDR.N R0,??DataTable7_1
192 /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */
193
194 /* USER CODE END TIM1_UP_TIM16_IRQn 0 */
195 HAL_TIM_IRQHandler(&htim1);
\ 0x2 0x.... LDR.N R0,??DataTable8_3
\ 0x4 0x.... 0x.... BL HAL_TIM_IRQHandler
195 HAL_TIM_IRQHandler(&htim16);
196 HAL_TIM_IRQHandler(&htim16);
\ 0x8 0xE8BD 0x4002 POP {R1,LR}
\ 0xC 0x.... LDR.N R0,??DataTable7_2
\ 0xC 0x.... LDR.N R0,??DataTable8_4
\ 0xE 0x.... 0x.... B.W HAL_TIM_IRQHandler
196 /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */
197
198 /* USER CODE END TIM1_UP_TIM16_IRQn 1 */
199 }
200
201 /**
202 * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
203 */
197 /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */
198
199 /* USER CODE END TIM1_UP_TIM16_IRQn 1 */
200 }
201
202 /**
203 * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
204 */
\ In section .text, align 2, keep-with-next
204 void TIM1_TRG_COM_TIM17_IRQHandler(void)
205 {
206 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
207
208 /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
209 HAL_TIM_IRQHandler(&htim17);
205 void TIM1_TRG_COM_TIM17_IRQHandler(void)
206 {
207 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
208
209 /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
210 HAL_TIM_IRQHandler(&htim17);
\ TIM1_TRG_COM_TIM17_IRQHandler: (+1)
\ 0x0 0x.... LDR.N R0,??DataTable7_3
\ 0x0 0x.... LDR.N R0,??DataTable8_5
\ 0x2 0x.... 0x.... B.W HAL_TIM_IRQHandler
210 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
211
212 /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
213 }
214
215 /**
216 * @brief This function handles USART1 global interrupt.
217 */
211 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
212
213 /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
214 }
215
216 /**
217 * @brief This function handles USART1 global interrupt.
218 */
\ In section .text, align 2, keep-with-next
218 void USART1_IRQHandler(void)
219 {
219 void USART1_IRQHandler(void)
220 {
\ USART1_IRQHandler: (+1)
\ 0x0 0xB538 PUSH {R3-R5,LR}
220 /* USER CODE BEGIN USART1_IRQn 0 */
221 uint8_t c = 0;
222 /* USER CODE END USART1_IRQn 0 */
223 HAL_UART_IRQHandler(&huart1);
\ 0x2 0x.... LDR.N R5,??DataTable7_4
\ 0x4 0x.... LDR.N R4,??DataTable7_5
221 /* USER CODE BEGIN USART1_IRQn 0 */
222 uint8_t c = 0;
223 /* USER CODE END USART1_IRQn 0 */
224 HAL_UART_IRQHandler(&huart1);
\ 0x2 0x.... LDR.N R5,??DataTable8_6
\ 0x4 0x.... LDR.N R4,??DataTable8_7
\ 0x6 0x4628 MOV R0,R5
\ 0x8 0x.... 0x.... BL HAL_UART_IRQHandler
224
225 HAL_UART_Receive_IT(&huart1, rx_uart1_buf,1);
225
226 HAL_UART_Receive_IT(&huart1, rx_uart1_buf,1);
\ 0xC 0x2201 MOVS R2,#+1
\ 0xE 0x4621 MOV R1,R4
\ 0x10 0x4628 MOV R0,R5
\ 0x12 0x.... 0x.... BL HAL_UART_Receive_IT
226 /* USER CODE BEGIN USART1_IRQn 1 */
227 uart_device_info *dev = (uart_device_info *)g_term_uart_handle;
\ 0x16 0x.... LDR.N R0,??DataTable7_6
227 /* USER CODE BEGIN USART1_IRQn 1 */
228 uart_device_info *dev = (uart_device_info *)g_term_uart_handle;
\ 0x16 0x.... LDR.N R0,??DataTable8_8
\ 0x18 0x6800 LDR R0,[R0, #+0]
228 c = rx_uart1_buf[0];
229
230 if(!RingQueueFull(&dev->uart_ring_queue))
229 c = rx_uart1_buf[0];
230
231 if(!RingQueueFull(&dev->uart_ring_queue))
^
Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined
in this statement
@ -362,43 +376,43 @@ Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined
\ 0x28 0x6902 LDR R2,[R0, #+16]
\ 0x2A 0x4291 CMP R1,R2
\ 0x2C 0xD005 BEQ.N ??USART1_IRQHandler_0
231 InRingQueue(&dev->uart_ring_queue, c);
232 InRingQueue(&dev->uart_ring_queue, c);
\ 0x2E 0x7821 LDRB R1,[R4, #+0]
\ 0x30 0xE8BD 0x4034 POP {R2,R4,R5,LR}
\ 0x34 0x3008 ADDS R0,R0,#+8
\ 0x36 0x.... 0x.... B.W InRingQueue
232
233
234 /* USER CODE END USART1_IRQn 1 */
235 }
233
234
235 /* USER CODE END USART1_IRQn 1 */
236 }
\ ??USART1_IRQHandler_0: (+1)
\ 0x3A 0xBD31 POP {R0,R4,R5,PC}
236
237 /**
238 * @brief This function handles USART3 global interrupt.
239 */
237
238 /**
239 * @brief This function handles USART3 global interrupt.
240 */
\ In section .text, align 2, keep-with-next
240 void USART3_IRQHandler(void)
241 {
241 void USART3_IRQHandler(void)
242 {
\ USART3_IRQHandler: (+1)
\ 0x0 0xB570 PUSH {R4-R6,LR}
242 /* USER CODE BEGIN USART3_IRQn 0 */
243 uint8_t c = 0;
244 /* USER CODE END USART3_IRQn 0 */
245 HAL_UART_IRQHandler(&huart3);
\ 0x2 0x.... LDR.N R6,??DataTable7_7
\ 0x4 0x.... LDR.N R5,??DataTable7_8
243 /* USER CODE BEGIN USART3_IRQn 0 */
244 uint8_t c = 0;
245 /* USER CODE END USART3_IRQn 0 */
246 HAL_UART_IRQHandler(&huart3);
\ 0x2 0x.... LDR.N R6,??DataTable8_9
\ 0x4 0x.... LDR.N R5,??DataTable8_10
\ 0x6 0x4630 MOV R0,R6
\ 0x8 0x.... 0x.... BL HAL_UART_IRQHandler
246 /* USER CODE BEGIN USART3_IRQn 1 */
247 uart_device_info *dev = (uart_device_info *)g_rs485_uart_handle;
\ 0xC 0x.... LDR.N R1,??DataTable7_9
247 /* USER CODE BEGIN USART3_IRQn 1 */
248 uart_device_info *dev = (uart_device_info *)g_rs485_uart_handle;
\ 0xC 0x.... LDR.N R1,??DataTable8_11
\ 0xE 0x.... 0x.... BL ?Subroutine2
248 HAL_UART_Receive_IT(&huart3, rx_uart3_buf,1);
249 c = rx_uart3_buf[0];
250
251 if(!RingQueueFull(&dev->uart_ring_queue))
249 HAL_UART_Receive_IT(&huart3, rx_uart3_buf,1);
250 c = rx_uart3_buf[0];
251
252 if(!RingQueueFull(&dev->uart_ring_queue))
^
Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined
in this statement
@ -406,10 +420,10 @@ Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined
\ 0x12 0x.... 0x.... BL ?Subroutine1
\ ??CrossCallReturnLabel_0: (+1)
\ 0x16 0xD000 BEQ.N ??USART3_IRQHandler_0
252 InRingQueue(&dev->uart_ring_queue, c);
253 InRingQueue(&dev->uart_ring_queue, c);
\ 0x18 0x.... B.N ?Subroutine0
253 /* USER CODE END USART3_IRQn 1 */
254 }
254 /* USER CODE END USART3_IRQn 1 */
255 }
\ ??USART3_IRQHandler_0: (+1)
\ 0x1A 0xBD70 POP {R4-R6,PC}
@ -438,32 +452,32 @@ Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined
\ 0x2 0xF104 0x0008 ADD R0,R4,#+8
\ 0x6 0xE8BD 0x4070 POP {R4-R6,LR}
\ 0xA 0x.... 0x.... B.W InRingQueue
255
256 /**
257 * @brief This function handles USART5 global interrupt.
258 */
256
257 /**
258 * @brief This function handles USART5 global interrupt.
259 */
\ In section .text, align 2, keep-with-next
259 void UART5_IRQHandler(void)
260 {
260 void UART5_IRQHandler(void)
261 {
\ UART5_IRQHandler: (+1)
\ 0x0 0xB570 PUSH {R4-R6,LR}
261 /* USER CODE BEGIN USART3_IRQn 0 */
262 uint8_t c = 0;
263 /* USER CODE END USART3_IRQn 0 */
264 HAL_UART_IRQHandler(&huart5);
\ 0x2 0x.... LDR.N R6,??DataTable7_10
\ 0x4 0x.... LDR.N R5,??DataTable7_11
262 /* USER CODE BEGIN USART3_IRQn 0 */
263 uint8_t c = 0;
264 /* USER CODE END USART3_IRQn 0 */
265 HAL_UART_IRQHandler(&huart5);
\ 0x2 0x.... LDR.N R6,??DataTable8_12
\ 0x4 0x.... LDR.N R5,??DataTable8_13
\ 0x6 0x4630 MOV R0,R6
\ 0x8 0x.... 0x.... BL HAL_UART_IRQHandler
265 /* USER CODE BEGIN USART3_IRQn 1 */
266 uart_device_info *dev = (uart_device_info *)g_ec801_uart_handle;
\ 0xC 0x.... LDR.N R1,??DataTable7_12
266 /* USER CODE BEGIN USART3_IRQn 1 */
267 uart_device_info *dev = (uart_device_info *)g_ec801_uart_handle;
\ 0xC 0x.... LDR.N R1,??DataTable8_14
\ 0xE 0x.... 0x.... BL ?Subroutine2
267 HAL_UART_Receive_IT(&huart5, rx_uart5_buf,1);
268 c = rx_uart5_buf[0];
269
270 if(!RingQueueFull(&dev->uart_ring_queue))
268 HAL_UART_Receive_IT(&huart5, rx_uart5_buf,1);
269 c = rx_uart5_buf[0];
270
271 if(!RingQueueFull(&dev->uart_ring_queue))
^
Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined
in this statement
@ -471,92 +485,100 @@ Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined
\ 0x12 0x.... 0x.... BL ?Subroutine1
\ ??CrossCallReturnLabel_1: (+1)
\ 0x16 0xD000 BEQ.N ??UART5_IRQHandler_0
271 InRingQueue(&dev->uart_ring_queue, c);
272 InRingQueue(&dev->uart_ring_queue, c);
\ 0x18 0x.... B.N ?Subroutine0
272 /* USER CODE END USART3_IRQn 1 */
273 }
273 /* USER CODE END USART3_IRQn 1 */
274 }
\ ??UART5_IRQHandler_0: (+1)
\ 0x1A 0xBD70 POP {R4-R6,PC}
274
275
276 /**
277 * @brief This function handles LPUART1 global interrupt.
278 */
276
277 /**
278 * @brief This function handles LPUART1 global interrupt.
279 */
\ In section .text, align 2, keep-with-next
279 void LPUART1_IRQHandler(void)
280 {
281 /* USER CODE BEGIN LPUART1_IRQn 0 */
282
283 /* USER CODE END LPUART1_IRQn 0 */
284 HAL_UART_IRQHandler(&hlpuart1);
280 void LPUART1_IRQHandler(void)
281 {
282 /* USER CODE BEGIN LPUART1_IRQn 0 */
283
284 /* USER CODE END LPUART1_IRQn 0 */
285 HAL_UART_IRQHandler(&hlpuart1);
\ LPUART1_IRQHandler: (+1)
\ 0x0 0x.... LDR.N R0,??DataTable7_13
\ 0x0 0x.... LDR.N R0,??DataTable8_15
\ 0x2 0x.... 0x.... B.W HAL_UART_IRQHandler
285 /* USER CODE BEGIN LPUART1_IRQn 1 */
286
287 /* USER CODE END LPUART1_IRQn 1 */
288 }
286 /* USER CODE BEGIN LPUART1_IRQn 1 */
287
288 /* USER CODE END LPUART1_IRQn 1 */
289 }
\ In section .text, align 4, keep-with-next
\ ??DataTable7:
\ ??DataTable8:
\ 0x0 0xE000'ED0C DC32 0xe000ed0c
\ In section .text, align 4, keep-with-next
\ ??DataTable8_1:
\ 0x0 0x05FA'0004 DC32 0x5fa0004
\ In section .text, align 4, keep-with-next
\ ??DataTable8_2:
\ 0x0 0x....'.... DC32 hdma_adc1
\ In section .text, align 4, keep-with-next
\ ??DataTable7_1:
\ ??DataTable8_3:
\ 0x0 0x....'.... DC32 htim1
\ In section .text, align 4, keep-with-next
\ ??DataTable7_2:
\ ??DataTable8_4:
\ 0x0 0x....'.... DC32 htim16
\ In section .text, align 4, keep-with-next
\ ??DataTable7_3:
\ ??DataTable8_5:
\ 0x0 0x....'.... DC32 htim17
\ In section .text, align 4, keep-with-next
\ ??DataTable7_4:
\ ??DataTable8_6:
\ 0x0 0x....'.... DC32 huart1
\ In section .text, align 4, keep-with-next
\ ??DataTable7_5:
\ ??DataTable8_7:
\ 0x0 0x....'.... DC32 rx_uart1_buf
\ In section .text, align 4, keep-with-next
\ ??DataTable7_6:
\ ??DataTable8_8:
\ 0x0 0x....'.... DC32 g_term_uart_handle
\ In section .text, align 4, keep-with-next
\ ??DataTable7_7:
\ ??DataTable8_9:
\ 0x0 0x....'.... DC32 huart3
\ In section .text, align 4, keep-with-next
\ ??DataTable7_8:
\ ??DataTable8_10:
\ 0x0 0x....'.... DC32 rx_uart3_buf
\ In section .text, align 4, keep-with-next
\ ??DataTable7_9:
\ ??DataTable8_11:
\ 0x0 0x....'.... DC32 g_rs485_uart_handle
\ In section .text, align 4, keep-with-next
\ ??DataTable7_10:
\ ??DataTable8_12:
\ 0x0 0x....'.... DC32 huart5
\ In section .text, align 4, keep-with-next
\ ??DataTable7_11:
\ ??DataTable8_13:
\ 0x0 0x....'.... DC32 rx_uart5_buf
\ In section .text, align 4, keep-with-next
\ ??DataTable7_12:
\ ??DataTable8_14:
\ 0x0 0x....'.... DC32 g_ec801_uart_handle
\ In section .text, align 4, keep-with-next
\ ??DataTable7_13:
\ ??DataTable8_15:
\ 0x0 0x....'.... DC32 hlpuart1
289
290 /* USER CODE BEGIN 1 */
291
292 /* USER CODE END 1 */
290
291 /* USER CODE BEGIN 1 */
292
293 /* USER CODE END 1 */
Maximum stack usage in bytes:
@ -595,27 +617,29 @@ Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined
Bytes Function/Label
----- --------------
4 ??DataTable7
4 ??DataTable7_1
4 ??DataTable7_10
4 ??DataTable7_11
4 ??DataTable7_12
4 ??DataTable7_13
4 ??DataTable7_2
4 ??DataTable7_3
4 ??DataTable7_4
4 ??DataTable7_5
4 ??DataTable7_6
4 ??DataTable7_7
4 ??DataTable7_8
4 ??DataTable7_9
4 ??DataTable8
4 ??DataTable8_1
4 ??DataTable8_10
4 ??DataTable8_11
4 ??DataTable8_12
4 ??DataTable8_13
4 ??DataTable8_14
4 ??DataTable8_15
4 ??DataTable8_2
4 ??DataTable8_3
4 ??DataTable8_4
4 ??DataTable8_5
4 ??DataTable8_6
4 ??DataTable8_7
4 ??DataTable8_8
4 ??DataTable8_9
14 ?Subroutine0
20 ?Subroutine1
12 ?Subroutine2
2 BusFault_Handler
6 DMA1_Channel1_IRQHandler
2 DebugMon_Handler
2 HardFault_Handler
32 HardFault_Handler
6 LPUART1_IRQHandler
2 MemManage_Handler
2 NMI_Handler
@ -627,9 +651,9 @@ Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined
2 UsageFault_Handler
266 bytes in section .text
304 bytes in section .text
266 bytes of CODE memory
304 bytes of CODE memory
Errors: none
Warnings: 3
Warnings: 4

524
EWARM/micro_climate/List/Core_13247989168731456611.dir/stm32l4xx_it.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:26:24
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb
@ -147,6 +147,44 @@
CFI DataAlign 4
CFI ReturnAddress R14 CODE
CFI CFA R13+0
CFI R0 Undefined
CFI R1 Undefined
CFI R2 Undefined
CFI R3 Undefined
CFI R4 SameValue
CFI R5 SameValue
CFI R6 SameValue
CFI R7 SameValue
CFI R8 SameValue
CFI R9 SameValue
CFI R10 SameValue
CFI R11 SameValue
CFI R12 Undefined
CFI R14 Undefined
CFI D0 Undefined
CFI D1 Undefined
CFI D2 Undefined
CFI D3 Undefined
CFI D4 Undefined
CFI D5 Undefined
CFI D6 Undefined
CFI D7 Undefined
CFI D8 SameValue
CFI D9 SameValue
CFI D10 SameValue
CFI D11 SameValue
CFI D12 SameValue
CFI D13 SameValue
CFI D14 SameValue
CFI D15 SameValue
CFI EndCommon cfiCommon1
CFI Common cfiCommon2 Using cfiNames0
CFI CodeAlign 2
CFI DataAlign 4
CFI ReturnAddress R14 CODE
CFI CFA R13+0
CFI R0 SameValue
CFI R1 SameValue
CFI R2 SameValue
@ -177,7 +215,7 @@
CFI D13 SameValue
CFI D14 SameValue
CFI D15 SameValue
CFI EndCommon cfiCommon1
CFI EndCommon cfiCommon2
// E:\Y\IAR\micro_climate\Core\Src\stm32l4xx_it.c
// 1 /* USER CODE BEGIN Header */
@ -286,251 +324,263 @@ NMI_Handler:
// 94 */
SECTION `.text`:CODE:NOROOT(1)
CFI Block cfiBlock1 Using cfiCommon0
CFI Block cfiBlock1 Using cfiCommon1
CFI Function HardFault_Handler
CFI NoCalls
THUMB
// 95 void HardFault_Handler(void)
// 96 {
// 97 /* USER CODE BEGIN HardFault_IRQn 0 */
// 98
// 99 /* USER CODE END HardFault_IRQn 0 */
// 100 while (1)
// 98 __iar_builtin_set_FAULTMASK(1);
HardFault_Handler:
MOVS R0,#+1
MSR FAULTMASK,R0
// 99 NVIC_SystemReset();
DSB SY
LDR.N R1,??DataTable8
LDR.N R0,??DataTable8_1
LDR R2,[R1, #+0]
AND R2,R2,#0x700
ORRS R2,R0,R2
STR R2,[R1, #+0]
DSB SY
??HardFault_Handler_0:
Nop
B.N ??HardFault_Handler_0
// 101 {
// 102 /* USER CODE BEGIN W1_HardFault_IRQn 0 */
// 103 /* USER CODE END W1_HardFault_IRQn 0 */
// 104 }
// 105 }
// 100 /* USER CODE END HardFault_IRQn 0 */
// 101 while (1)
// 102 {
// 103 /* USER CODE BEGIN W1_HardFault_IRQn 0 */
// 104 /* USER CODE END W1_HardFault_IRQn 0 */
// 105 }
// 106 }
CFI EndBlock cfiBlock1
// 106
// 107 /**
// 108 * @brief This function handles Memory management fault.
// 109 */
// 107
// 108 /**
// 109 * @brief This function handles Memory management fault.
// 110 */
SECTION `.text`:CODE:NOROOT(1)
CFI Block cfiBlock2 Using cfiCommon0
CFI Function MemManage_Handler
CFI NoCalls
THUMB
// 110 void MemManage_Handler(void)
// 111 {
// 112 /* USER CODE BEGIN MemoryManagement_IRQn 0 */
// 113
// 114 /* USER CODE END MemoryManagement_IRQn 0 */
// 115 while (1)
// 111 void MemManage_Handler(void)
// 112 {
// 113 /* USER CODE BEGIN MemoryManagement_IRQn 0 */
// 114
// 115 /* USER CODE END MemoryManagement_IRQn 0 */
// 116 while (1)
MemManage_Handler:
??MemManage_Handler_0:
B.N ??MemManage_Handler_0
// 116 {
// 117 /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
// 118 /* USER CODE END W1_MemoryManagement_IRQn 0 */
// 119 }
// 120 }
// 117 {
// 118 /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
// 119 /* USER CODE END W1_MemoryManagement_IRQn 0 */
// 120 }
// 121 }
CFI EndBlock cfiBlock2
// 121
// 122 /**
// 123 * @brief This function handles Prefetch fault, memory access fault.
// 124 */
// 122
// 123 /**
// 124 * @brief This function handles Prefetch fault, memory access fault.
// 125 */
SECTION `.text`:CODE:NOROOT(1)
CFI Block cfiBlock3 Using cfiCommon0
CFI Function BusFault_Handler
CFI NoCalls
THUMB
// 125 void BusFault_Handler(void)
// 126 {
// 127 /* USER CODE BEGIN BusFault_IRQn 0 */
// 128
// 129 /* USER CODE END BusFault_IRQn 0 */
// 130 while (1)
// 126 void BusFault_Handler(void)
// 127 {
// 128 /* USER CODE BEGIN BusFault_IRQn 0 */
// 129
// 130 /* USER CODE END BusFault_IRQn 0 */
// 131 while (1)
BusFault_Handler:
??BusFault_Handler_0:
B.N ??BusFault_Handler_0
// 131 {
// 132 /* USER CODE BEGIN W1_BusFault_IRQn 0 */
// 133 /* USER CODE END W1_BusFault_IRQn 0 */
// 134 }
// 135 }
// 132 {
// 133 /* USER CODE BEGIN W1_BusFault_IRQn 0 */
// 134 /* USER CODE END W1_BusFault_IRQn 0 */
// 135 }
// 136 }
CFI EndBlock cfiBlock3
// 136
// 137 /**
// 138 * @brief This function handles Undefined instruction or illegal state.
// 139 */
// 137
// 138 /**
// 139 * @brief This function handles Undefined instruction or illegal state.
// 140 */
SECTION `.text`:CODE:NOROOT(1)
CFI Block cfiBlock4 Using cfiCommon0
CFI Function UsageFault_Handler
CFI NoCalls
THUMB
// 140 void UsageFault_Handler(void)
// 141 {
// 142 /* USER CODE BEGIN UsageFault_IRQn 0 */
// 143
// 144 /* USER CODE END UsageFault_IRQn 0 */
// 145 while (1)
// 141 void UsageFault_Handler(void)
// 142 {
// 143 /* USER CODE BEGIN UsageFault_IRQn 0 */
// 144
// 145 /* USER CODE END UsageFault_IRQn 0 */
// 146 while (1)
UsageFault_Handler:
??UsageFault_Handler_0:
B.N ??UsageFault_Handler_0
// 146 {
// 147 /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
// 148 /* USER CODE END W1_UsageFault_IRQn 0 */
// 149 }
// 150 }
// 147 {
// 148 /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
// 149 /* USER CODE END W1_UsageFault_IRQn 0 */
// 150 }
// 151 }
CFI EndBlock cfiBlock4
// 151
// 152 /**
// 153 * @brief This function handles Debug monitor.
// 154 */
// 152
// 153 /**
// 154 * @brief This function handles Debug monitor.
// 155 */
SECTION `.text`:CODE:NOROOT(1)
CFI Block cfiBlock5 Using cfiCommon0
CFI Function DebugMon_Handler
CFI NoCalls
THUMB
// 155 void DebugMon_Handler(void)
// 156 {
// 157 /* USER CODE BEGIN DebugMonitor_IRQn 0 */
// 158
// 159 /* USER CODE END DebugMonitor_IRQn 0 */
// 160 /* USER CODE BEGIN DebugMonitor_IRQn 1 */
// 161
// 162 /* USER CODE END DebugMonitor_IRQn 1 */
// 163 }
// 156 void DebugMon_Handler(void)
// 157 {
// 158 /* USER CODE BEGIN DebugMonitor_IRQn 0 */
// 159
// 160 /* USER CODE END DebugMonitor_IRQn 0 */
// 161 /* USER CODE BEGIN DebugMonitor_IRQn 1 */
// 162
// 163 /* USER CODE END DebugMonitor_IRQn 1 */
// 164 }
DebugMon_Handler:
BX LR
CFI EndBlock cfiBlock5
// 164
// 165 /******************************************************************************/
// 166 /* STM32L4xx Peripheral Interrupt Handlers */
// 167 /* Add here the Interrupt Handlers for the used peripherals. */
// 168 /* For the available peripheral interrupt handler names, */
// 169 /* please refer to the startup file (startup_stm32l4xx.s). */
// 170 /******************************************************************************/
// 171
// 172 /**
// 173 * @brief This function handles DMA1 channel1 global interrupt.
// 174 */
// 165
// 166 /******************************************************************************/
// 167 /* STM32L4xx Peripheral Interrupt Handlers */
// 168 /* Add here the Interrupt Handlers for the used peripherals. */
// 169 /* For the available peripheral interrupt handler names, */
// 170 /* please refer to the startup file (startup_stm32l4xx.s). */
// 171 /******************************************************************************/
// 172
// 173 /**
// 174 * @brief This function handles DMA1 channel1 global interrupt.
// 175 */
SECTION `.text`:CODE:NOROOT(1)
CFI Block cfiBlock6 Using cfiCommon0
CFI Function DMA1_Channel1_IRQHandler
THUMB
// 175 void DMA1_Channel1_IRQHandler(void)
// 176 {
// 177 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
// 178
// 179 /* USER CODE END DMA1_Channel1_IRQn 0 */
// 180 HAL_DMA_IRQHandler(&hdma_adc1);
// 176 void DMA1_Channel1_IRQHandler(void)
// 177 {
// 178 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
// 179
// 180 /* USER CODE END DMA1_Channel1_IRQn 0 */
// 181 HAL_DMA_IRQHandler(&hdma_adc1);
DMA1_Channel1_IRQHandler:
LDR.N R0,??DataTable7
LDR.N R0,??DataTable8_2
CFI FunCall HAL_DMA_IRQHandler
B.W HAL_DMA_IRQHandler
// 181 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
// 182
// 183 /* USER CODE END DMA1_Channel1_IRQn 1 */
// 184 }
// 182 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
// 183
// 184 /* USER CODE END DMA1_Channel1_IRQn 1 */
// 185 }
CFI EndBlock cfiBlock6
// 185
// 186 /**
// 187 * @brief This function handles TIM1 update interrupt and TIM16 global interrupt.
// 188 */
// 186
// 187 /**
// 188 * @brief This function handles TIM1 update interrupt and TIM16 global interrupt.
// 189 */
SECTION `.text`:CODE:NOROOT(1)
CFI Block cfiBlock7 Using cfiCommon0
CFI Function TIM1_UP_TIM16_IRQHandler
THUMB
// 189 void TIM1_UP_TIM16_IRQHandler(void)
// 190 {
// 190 void TIM1_UP_TIM16_IRQHandler(void)
// 191 {
TIM1_UP_TIM16_IRQHandler:
PUSH {R7,LR}
CFI R14 Frame(CFA, -4)
CFI CFA R13+8
// 191 /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */
// 192
// 193 /* USER CODE END TIM1_UP_TIM16_IRQn 0 */
// 194 HAL_TIM_IRQHandler(&htim1);
LDR.N R0,??DataTable7_1
// 192 /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */
// 193
// 194 /* USER CODE END TIM1_UP_TIM16_IRQn 0 */
// 195 HAL_TIM_IRQHandler(&htim1);
LDR.N R0,??DataTable8_3
CFI FunCall HAL_TIM_IRQHandler
BL HAL_TIM_IRQHandler
// 195 HAL_TIM_IRQHandler(&htim16);
// 196 HAL_TIM_IRQHandler(&htim16);
POP {R1,LR}
CFI R14 SameValue
CFI CFA R13+0
LDR.N R0,??DataTable7_2
LDR.N R0,??DataTable8_4
CFI FunCall HAL_TIM_IRQHandler
B.W HAL_TIM_IRQHandler
// 196 /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */
// 197
// 198 /* USER CODE END TIM1_UP_TIM16_IRQn 1 */
// 199 }
// 197 /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */
// 198
// 199 /* USER CODE END TIM1_UP_TIM16_IRQn 1 */
// 200 }
CFI EndBlock cfiBlock7
// 200
// 201 /**
// 202 * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
// 203 */
// 201
// 202 /**
// 203 * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
// 204 */
SECTION `.text`:CODE:NOROOT(1)
CFI Block cfiBlock8 Using cfiCommon0
CFI Function TIM1_TRG_COM_TIM17_IRQHandler
THUMB
// 204 void TIM1_TRG_COM_TIM17_IRQHandler(void)
// 205 {
// 206 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
// 207
// 208 /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
// 209 HAL_TIM_IRQHandler(&htim17);
// 205 void TIM1_TRG_COM_TIM17_IRQHandler(void)
// 206 {
// 207 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
// 208
// 209 /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
// 210 HAL_TIM_IRQHandler(&htim17);
TIM1_TRG_COM_TIM17_IRQHandler:
LDR.N R0,??DataTable7_3
LDR.N R0,??DataTable8_5
CFI FunCall HAL_TIM_IRQHandler
B.W HAL_TIM_IRQHandler
// 210 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
// 211
// 212 /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
// 213 }
// 211 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
// 212
// 213 /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
// 214 }
CFI EndBlock cfiBlock8
// 214
// 215 /**
// 216 * @brief This function handles USART1 global interrupt.
// 217 */
// 215
// 216 /**
// 217 * @brief This function handles USART1 global interrupt.
// 218 */
SECTION `.text`:CODE:NOROOT(1)
CFI Block cfiBlock9 Using cfiCommon0
CFI Function USART1_IRQHandler
THUMB
// 218 void USART1_IRQHandler(void)
// 219 {
// 219 void USART1_IRQHandler(void)
// 220 {
USART1_IRQHandler:
PUSH {R3-R5,LR}
CFI R14 Frame(CFA, -4)
CFI R5 Frame(CFA, -8)
CFI R4 Frame(CFA, -12)
CFI CFA R13+16
// 220 /* USER CODE BEGIN USART1_IRQn 0 */
// 221 uint8_t c = 0;
// 222 /* USER CODE END USART1_IRQn 0 */
// 223 HAL_UART_IRQHandler(&huart1);
LDR.N R5,??DataTable7_4
LDR.N R4,??DataTable7_5
// 221 /* USER CODE BEGIN USART1_IRQn 0 */
// 222 uint8_t c = 0;
// 223 /* USER CODE END USART1_IRQn 0 */
// 224 HAL_UART_IRQHandler(&huart1);
LDR.N R5,??DataTable8_6
LDR.N R4,??DataTable8_7
MOV R0,R5
CFI FunCall HAL_UART_IRQHandler
BL HAL_UART_IRQHandler
// 224
// 225 HAL_UART_Receive_IT(&huart1, rx_uart1_buf,1);
// 225
// 226 HAL_UART_Receive_IT(&huart1, rx_uart1_buf,1);
MOVS R2,#+1
MOV R1,R4
MOV R0,R5
CFI FunCall HAL_UART_Receive_IT
BL HAL_UART_Receive_IT
// 226 /* USER CODE BEGIN USART1_IRQn 1 */
// 227 uart_device_info *dev = (uart_device_info *)g_term_uart_handle;
LDR.N R0,??DataTable7_6
// 227 /* USER CODE BEGIN USART1_IRQn 1 */
// 228 uart_device_info *dev = (uart_device_info *)g_term_uart_handle;
LDR.N R0,??DataTable8_8
LDR R0,[R0, #+0]
// 228 c = rx_uart1_buf[0];
// 229
// 230 if(!RingQueueFull(&dev->uart_ring_queue))
// 229 c = rx_uart1_buf[0];
// 230
// 231 if(!RingQueueFull(&dev->uart_ring_queue))
LDR R1,[R0, #+20]
LDR R2,[R0, #+12]
ADDS R1,R1,#+1
@ -539,7 +589,7 @@ USART1_IRQHandler:
LDR R2,[R0, #+16]
CMP R1,R2
BEQ.N ??USART1_IRQHandler_0
// 231 InRingQueue(&dev->uart_ring_queue, c);
// 232 InRingQueue(&dev->uart_ring_queue, c);
LDRB R1,[R4, #+0]
POP {R2,R4,R5,LR}
CFI R4 SameValue
@ -553,24 +603,24 @@ USART1_IRQHandler:
CFI R5 Frame(CFA, -8)
CFI R14 Frame(CFA, -4)
CFI CFA R13+16
// 232
// 233
// 234 /* USER CODE END USART1_IRQn 1 */
// 235 }
// 233
// 234
// 235 /* USER CODE END USART1_IRQn 1 */
// 236 }
??USART1_IRQHandler_0:
POP {R0,R4,R5,PC}
CFI EndBlock cfiBlock9
// 236
// 237 /**
// 238 * @brief This function handles USART3 global interrupt.
// 239 */
// 237
// 238 /**
// 239 * @brief This function handles USART3 global interrupt.
// 240 */
SECTION `.text`:CODE:NOROOT(1)
CFI Block cfiBlock10 Using cfiCommon0
CFI Function USART3_IRQHandler
THUMB
// 240 void USART3_IRQHandler(void)
// 241 {
// 241 void USART3_IRQHandler(void)
// 242 {
USART3_IRQHandler:
PUSH {R4-R6,LR}
CFI R14 Frame(CFA, -4)
@ -578,45 +628,45 @@ USART3_IRQHandler:
CFI R5 Frame(CFA, -12)
CFI R4 Frame(CFA, -16)
CFI CFA R13+16
// 242 /* USER CODE BEGIN USART3_IRQn 0 */
// 243 uint8_t c = 0;
// 244 /* USER CODE END USART3_IRQn 0 */
// 245 HAL_UART_IRQHandler(&huart3);
LDR.N R6,??DataTable7_7
LDR.N R5,??DataTable7_8
// 243 /* USER CODE BEGIN USART3_IRQn 0 */
// 244 uint8_t c = 0;
// 245 /* USER CODE END USART3_IRQn 0 */
// 246 HAL_UART_IRQHandler(&huart3);
LDR.N R6,??DataTable8_9
LDR.N R5,??DataTable8_10
MOV R0,R6
CFI FunCall HAL_UART_IRQHandler
BL HAL_UART_IRQHandler
// 246 /* USER CODE BEGIN USART3_IRQn 1 */
// 247 uart_device_info *dev = (uart_device_info *)g_rs485_uart_handle;
LDR.N R1,??DataTable7_9
// 247 /* USER CODE BEGIN USART3_IRQn 1 */
// 248 uart_device_info *dev = (uart_device_info *)g_rs485_uart_handle;
LDR.N R1,??DataTable8_11
BL ?Subroutine2
// 248 HAL_UART_Receive_IT(&huart3, rx_uart3_buf,1);
// 249 c = rx_uart3_buf[0];
// 250
// 251 if(!RingQueueFull(&dev->uart_ring_queue))
// 249 HAL_UART_Receive_IT(&huart3, rx_uart3_buf,1);
// 250 c = rx_uart3_buf[0];
// 251
// 252 if(!RingQueueFull(&dev->uart_ring_queue))
??CrossCallReturnLabel_3:
BL ?Subroutine1
??CrossCallReturnLabel_0:
BEQ.N ??USART3_IRQHandler_0
// 252 InRingQueue(&dev->uart_ring_queue, c);
// 253 InRingQueue(&dev->uart_ring_queue, c);
B.N ?Subroutine0
// 253 /* USER CODE END USART3_IRQn 1 */
// 254 }
// 254 /* USER CODE END USART3_IRQn 1 */
// 255 }
??USART3_IRQHandler_0:
POP {R4-R6,PC}
CFI EndBlock cfiBlock10
// 255
// 256 /**
// 257 * @brief This function handles USART5 global interrupt.
// 258 */
// 256
// 257 /**
// 258 * @brief This function handles USART5 global interrupt.
// 259 */
SECTION `.text`:CODE:NOROOT(1)
CFI Block cfiBlock11 Using cfiCommon0
CFI Function UART5_IRQHandler
THUMB
// 259 void UART5_IRQHandler(void)
// 260 {
// 260 void UART5_IRQHandler(void)
// 261 {
UART5_IRQHandler:
PUSH {R4-R6,LR}
CFI R14 Frame(CFA, -4)
@ -624,31 +674,31 @@ UART5_IRQHandler:
CFI R5 Frame(CFA, -12)
CFI R4 Frame(CFA, -16)
CFI CFA R13+16
// 261 /* USER CODE BEGIN USART3_IRQn 0 */
// 262 uint8_t c = 0;
// 263 /* USER CODE END USART3_IRQn 0 */
// 264 HAL_UART_IRQHandler(&huart5);
LDR.N R6,??DataTable7_10
LDR.N R5,??DataTable7_11
// 262 /* USER CODE BEGIN USART3_IRQn 0 */
// 263 uint8_t c = 0;
// 264 /* USER CODE END USART3_IRQn 0 */
// 265 HAL_UART_IRQHandler(&huart5);
LDR.N R6,??DataTable8_12
LDR.N R5,??DataTable8_13
MOV R0,R6
CFI FunCall HAL_UART_IRQHandler
BL HAL_UART_IRQHandler
// 265 /* USER CODE BEGIN USART3_IRQn 1 */
// 266 uart_device_info *dev = (uart_device_info *)g_ec801_uart_handle;
LDR.N R1,??DataTable7_12
// 266 /* USER CODE BEGIN USART3_IRQn 1 */
// 267 uart_device_info *dev = (uart_device_info *)g_ec801_uart_handle;
LDR.N R1,??DataTable8_14
BL ?Subroutine2
// 267 HAL_UART_Receive_IT(&huart5, rx_uart5_buf,1);
// 268 c = rx_uart5_buf[0];
// 269
// 270 if(!RingQueueFull(&dev->uart_ring_queue))
// 268 HAL_UART_Receive_IT(&huart5, rx_uart5_buf,1);
// 269 c = rx_uart5_buf[0];
// 270
// 271 if(!RingQueueFull(&dev->uart_ring_queue))
??CrossCallReturnLabel_2:
BL ?Subroutine1
??CrossCallReturnLabel_1:
BEQ.N ??UART5_IRQHandler_0
// 271 InRingQueue(&dev->uart_ring_queue, c);
// 272 InRingQueue(&dev->uart_ring_queue, c);
B.N ?Subroutine0
// 272 /* USER CODE END USART3_IRQn 1 */
// 273 }
// 273 /* USER CODE END USART3_IRQn 1 */
// 274 }
??UART5_IRQHandler_0:
POP {R4-R6,PC}
CFI EndBlock cfiBlock11
@ -670,7 +720,7 @@ UART5_IRQHandler:
CFI (cfiCond13) R6 Frame(CFA, -8)
CFI (cfiCond13) R14 Frame(CFA, -4)
CFI (cfiCond13) CFA R13+16
CFI Block cfiPicker14 Using cfiCommon1
CFI Block cfiPicker14 Using cfiCommon2
CFI (cfiPicker14) NoFunction
CFI (cfiPicker14) Picker
THUMB
@ -703,7 +753,7 @@ UART5_IRQHandler:
CFI (cfiCond16) R6 Frame(CFA, -8)
CFI (cfiCond16) R14 Frame(CFA, -4)
CFI (cfiCond16) CFA R13+16
CFI Block cfiPicker17 Using cfiCommon1
CFI Block cfiPicker17 Using cfiCommon2
CFI (cfiPicker17) NoFunction
CFI (cfiPicker17) Picker
THUMB
@ -742,127 +792,141 @@ UART5_IRQHandler:
CFI FunCall UART5_IRQHandler InRingQueue
B.W InRingQueue
CFI EndBlock cfiBlock18
// 274
// 275
// 276 /**
// 277 * @brief This function handles LPUART1 global interrupt.
// 278 */
// 276
// 277 /**
// 278 * @brief This function handles LPUART1 global interrupt.
// 279 */
SECTION `.text`:CODE:NOROOT(1)
CFI Block cfiBlock19 Using cfiCommon0
CFI Function LPUART1_IRQHandler
THUMB
// 279 void LPUART1_IRQHandler(void)
// 280 {
// 281 /* USER CODE BEGIN LPUART1_IRQn 0 */
// 282
// 283 /* USER CODE END LPUART1_IRQn 0 */
// 284 HAL_UART_IRQHandler(&hlpuart1);
// 280 void LPUART1_IRQHandler(void)
// 281 {
// 282 /* USER CODE BEGIN LPUART1_IRQn 0 */
// 283
// 284 /* USER CODE END LPUART1_IRQn 0 */
// 285 HAL_UART_IRQHandler(&hlpuart1);
LPUART1_IRQHandler:
LDR.N R0,??DataTable7_13
LDR.N R0,??DataTable8_15
CFI FunCall HAL_UART_IRQHandler
B.W HAL_UART_IRQHandler
// 285 /* USER CODE BEGIN LPUART1_IRQn 1 */
// 286
// 287 /* USER CODE END LPUART1_IRQn 1 */
// 288 }
// 286 /* USER CODE BEGIN LPUART1_IRQn 1 */
// 287
// 288 /* USER CODE END LPUART1_IRQn 1 */
// 289 }
CFI EndBlock cfiBlock19
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable7:
??DataTable8:
DATA32
DC32 0xe000ed0c
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable8_1:
DATA32
DC32 0x5fa0004
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable8_2:
DATA32
DC32 hdma_adc1
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable7_1:
??DataTable8_3:
DATA32
DC32 htim1
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable7_2:
??DataTable8_4:
DATA32
DC32 htim16
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable7_3:
??DataTable8_5:
DATA32
DC32 htim17
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable7_4:
??DataTable8_6:
DATA32
DC32 huart1
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable7_5:
??DataTable8_7:
DATA32
DC32 rx_uart1_buf
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable7_6:
??DataTable8_8:
DATA32
DC32 g_term_uart_handle
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable7_7:
??DataTable8_9:
DATA32
DC32 huart3
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable7_8:
??DataTable8_10:
DATA32
DC32 rx_uart3_buf
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable7_9:
??DataTable8_11:
DATA32
DC32 g_rs485_uart_handle
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable7_10:
??DataTable8_12:
DATA32
DC32 huart5
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable7_11:
??DataTable8_13:
DATA32
DC32 rx_uart5_buf
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable7_12:
??DataTable8_14:
DATA32
DC32 g_ec801_uart_handle
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable7_13:
??DataTable8_15:
DATA32
DC32 hlpuart1
@ -872,14 +936,14 @@ LPUART1_IRQHandler:
DC32 0
END
// 289
// 290 /* USER CODE BEGIN 1 */
// 291
// 292 /* USER CODE END 1 */
// 290
// 291 /* USER CODE BEGIN 1 */
// 292
// 293 /* USER CODE END 1 */
//
// 266 bytes in section .text
// 304 bytes in section .text
//
// 266 bytes of CODE memory
// 304 bytes of CODE memory
//
//Errors: none
//Warnings: 3
//Warnings: 4

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/tim.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:02
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/tim.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:02
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/usart.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/Core_13247989168731456611.dir/usart.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/EC801E_17758034221153603070.dir/EC801E.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/EC801E_17758034221153603070.dir/EC801E.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/EWARM_18443280873093131863.dir/startup_stm32l496xx.lst
View File

@ -2,7 +2,7 @@
###############################################################################
# #
# IAR Assembler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:06 #
# IAR Assembler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56 #
# Copyright 1999-2023 IAR Systems AB. #
# #
# Source file = E:\Y\IAR\micro_climate\EWARM\startup_stm32l496xx.s#

2
EWARM/micro_climate/List/Filter_2427836196881467961.dir/filter.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:02
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/Filter_2427836196881467961.dir/filter.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:02
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/cmsis_os.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:05
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:55
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/cmsis_os.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:05
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:55
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/croutine.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:05
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/croutine.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:05
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/event_groups.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:06
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/event_groups.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:06
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/heap_4.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:06
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/heap_4.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:06
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/list.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:06
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/list.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:06
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/port.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:06
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/port.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:06
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/portasm.lst
View File

@ -2,7 +2,7 @@
###############################################################################
# #
# IAR Assembler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:06 #
# IAR Assembler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56 #
# Copyright 1999-2023 IAR Systems AB. #
# #
# Source file = E:\Y\IAR\micro_climate\Middlewares\Third_Party\FreeRTOS\Source\portable\IAR\ARM_CM4F\portasm.s#

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/queue.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:07
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/queue.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:07
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/stream_buffer.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:07
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/stream_buffer.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:07
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/tasks.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:07
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:57
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/tasks.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:07
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:57
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/timers.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/FreeRTOS_4809373609813369194.dir/timers.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:56
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/HP203B_1856951872026386537.dir/hp203b.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/HP203B_1856951872026386537.dir/hp203b.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/RingQueue_10900368326811202236.dir/ring_queue.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/RingQueue_10900368326811202236.dir/ring_queue.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:53
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:03
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_adc.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:55
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_adc.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:55
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_adc_ex.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_adc_ex.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_cortex.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_cortex.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_dma.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_dma.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_dma_ex.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_dma_ex.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_exti.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_exti.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_flash.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_flash.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_flash_ex.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_flash_ex.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_flash_ramfunc.lst
View File

@ -1,6 +1,6 @@
###############################################################################
#
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
# IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
# Copyright 1999-2023 IAR Systems AB.
#
# Cpu mode = thumb

2
EWARM/micro_climate/List/STM32L4xx_HAL_Driver_2987639196379523013.dir/stm32l4xx_hal_flash_ramfunc.s
View File

@ -1,6 +1,6 @@
///////////////////////////////////////////////////////////////////////////////
//
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 20/Sep/2024 09:29:04
// IAR ANSI C/C++ Compiler V9.40.2.374/W64 for ARM 21/Sep/2024 11:22:54
// Copyright 1999-2023 IAR Systems AB.
//
// Cpu mode = thumb

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