1049 lines
58 KiB
C
1049 lines
58 KiB
C
/**
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******************************************************************************
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* @file stm32l4xx_hal_ospi.h
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* @author MCD Application Team
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* @brief Header file of OSPI HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32L4xx_HAL_OSPI_H
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#define STM32L4xx_HAL_OSPI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l4xx_hal_def.h"
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#if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2)
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/** @addtogroup STM32L4xx_HAL_Driver
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* @{
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*/
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/** @addtogroup OSPI
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup OSPI_Exported_Types OSPI Exported Types
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* @{
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*/
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/**
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* @brief OSPI Init structure definition
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*/
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typedef struct
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{
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uint32_t FifoThreshold; /*!< This is the threshold used by the Peripheral to generate the interrupt
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indicating that data are available in reception or free place
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is available in transmission.
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This parameter can be a value between 1 and 32 */
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uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to access up to
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quad mode on two different devices to increase the throughput.
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This parameter can be a value of @ref OSPI_DualQuad */
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uint32_t MemoryType; /*!< It indicates the external device type connected to the OSPI.
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This parameter can be a value of @ref OSPI_MemoryType */
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uint32_t DeviceSize; /*!< It defines the size of the external device connected to the OSPI,
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it corresponds to the number of address bits required to access
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the external device.
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This parameter can be a value between 1 and 32 */
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uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select
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must remain high between commands.
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This parameter can be a value between 1 and 8 */
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uint32_t FreeRunningClock; /*!< It enables or not the free running clock.
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This parameter can be a value of @ref OSPI_FreeRunningClock */
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uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released.
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This parameter can be a value of @ref OSPI_ClockMode */
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uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating
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the external clock based on the AHB clock.
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This parameter can be a value between 1 and 256 */
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uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order
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to take in account external signal delays.
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This parameter can be a value of @ref OSPI_SampleShifting */
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uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data.
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This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */
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uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and
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defines the boundary of bytes to release the chip select.
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This parameter can be a value between 0 and 31 */
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uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected
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by the delay block.
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This parameter can be a value of @ref OSPI_DelayBlockBypass */
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#if defined (OCTOSPI_DCR3_MAXTRAN)
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uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is
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released every MaxTran+1 bytes when the other OctoSPI request the access
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to the bus.
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This parameter can be a value between 0 and 255 */
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#endif
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#if defined (OCTOSPI_DCR4_REFRESH)
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uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every
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Refresh+1 clock cycles.
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This parameter can be a value between 0 and 0xFFFFFFFF */
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#endif
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} OSPI_InitTypeDef;
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/**
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* @brief HAL OSPI Handle Structure definition
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*/
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#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
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typedef struct __OSPI_HandleTypeDef
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#else
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typedef struct
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#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
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{
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OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */
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OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */
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uint8_t *pBuffPtr; /*!< Address of the OSPI buffer for transfer */
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__IO uint32_t XferSize; /*!< Number of data to transfer */
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__IO uint32_t XferCount; /*!< Counter of data transferred */
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DMA_HandleTypeDef *hdma; /*!< Handle of the DMA channel used for the transfer */
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__IO uint32_t State; /*!< Internal state of the OSPI HAL driver */
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__IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */
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uint32_t Timeout; /*!< Timeout used for the OSPI external device access */
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#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
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void (* ErrorCallback)(struct __OSPI_HandleTypeDef *hospi);
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void (* AbortCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
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void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi);
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void (* CmdCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
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void (* RxCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
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void (* TxCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
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void (* RxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
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void (* TxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
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void (* StatusMatchCallback)(struct __OSPI_HandleTypeDef *hospi);
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void (* TimeOutCallback)(struct __OSPI_HandleTypeDef *hospi);
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void (* MspInitCallback)(struct __OSPI_HandleTypeDef *hospi);
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void (* MspDeInitCallback)(struct __OSPI_HandleTypeDef *hospi);
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#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
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} OSPI_HandleTypeDef;
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/**
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* @brief HAL OSPI Regular Command Structure definition
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*/
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typedef struct
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{
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uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or
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to the registers for the write operation (these registers are only
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used for memory-mapped mode).
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This parameter can be a value of @ref OSPI_OperationType */
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uint32_t FlashId; /*!< It indicates which external device is selected for this command (it
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applies only if Dualquad is disabled in the initialization structure).
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This parameter can be a value of @ref OSPI_FlashID */
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uint32_t Instruction; /*!< It contains the instruction to be sent to the device.
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This parameter can be a value between 0 and 0xFFFFFFFF */
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uint32_t InstructionMode; /*!< It indicates the mode of the instruction.
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This parameter can be a value of @ref OSPI_InstructionMode */
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uint32_t InstructionSize; /*!< It indicates the size of the instruction.
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This parameter can be a value of @ref OSPI_InstructionSize */
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uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase.
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This parameter can be a value of @ref OSPI_InstructionDtrMode */
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uint32_t Address; /*!< It contains the address to be sent to the device.
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This parameter can be a value between 0 and 0xFFFFFFFF */
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uint32_t AddressMode; /*!< It indicates the mode of the address.
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This parameter can be a value of @ref OSPI_AddressMode */
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uint32_t AddressSize; /*!< It indicates the size of the address.
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This parameter can be a value of @ref OSPI_AddressSize */
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uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase.
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This parameter can be a value of @ref OSPI_AddressDtrMode */
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uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device.
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This parameter can be a value between 0 and 0xFFFFFFFF */
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uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes.
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This parameter can be a value of @ref OSPI_AlternateBytesMode */
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uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes.
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This parameter can be a value of @ref OSPI_AlternateBytesSize */
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uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase.
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This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */
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uint32_t DataMode; /*!< It indicates the mode of the data.
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This parameter can be a value of @ref OSPI_DataMode */
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uint32_t NbData; /*!< It indicates the number of data transferred with this command.
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This field is only used for indirect mode.
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This parameter can be a value between 1 and 0xFFFFFFFF */
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uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase.
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This parameter can be a value of @ref OSPI_DataDtrMode */
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uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase.
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This parameter can be a value between 0 and 31 */
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uint32_t DQSMode; /*!< It enables or not the data strobe management.
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This parameter can be a value of @ref OSPI_DQSMode */
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uint32_t SIOOMode; /*!< It enables or not the SIOO mode.
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This parameter can be a value of @ref OSPI_SIOOMode */
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} OSPI_RegularCmdTypeDef;
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/**
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* @brief HAL OSPI Hyperbus Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time.
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This parameter can be a value between 0 and 255 */
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uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time.
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This parameter can be a value between 0 and 255 */
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uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access.
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This parameter can be a value of @ref OSPI_WriteZeroLatency */
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uint32_t LatencyMode; /*!< It configures the latency mode.
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This parameter can be a value of @ref OSPI_LatencyMode */
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} OSPI_HyperbusCfgTypeDef;
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/**
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* @brief HAL OSPI Hyperbus Command Structure definition
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*/
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typedef struct
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{
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uint32_t AddressSpace; /*!< It indicates the address space accessed by the command.
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This parameter can be a value of @ref OSPI_AddressSpace */
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uint32_t Address; /*!< It contains the address to be sent tot he device.
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This parameter can be a value between 0 and 0xFFFFFFFF */
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uint32_t AddressSize; /*!< It indicates the size of the address.
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This parameter can be a value of @ref OSPI_AddressSize */
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uint32_t NbData; /*!< It indicates the number of data transferred with this command.
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This field is only used for indirect mode.
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This parameter can be a value between 1 and 0xFFFFFFFF
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In case of autopolling mode, this parameter can be any value between 1 and 4 */
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uint32_t DQSMode; /*!< It enables or not the data strobe management.
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This parameter can be a value of @ref OSPI_DQSMode */
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} OSPI_HyperbusCmdTypeDef;
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/**
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* @brief HAL OSPI Auto Polling mode configuration structure definition
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*/
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typedef struct
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{
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uint32_t Match; /*!< Specifies the value to be compared with the masked status register to get a match.
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This parameter can be any value between 0 and 0xFFFFFFFF */
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uint32_t Mask; /*!< Specifies the mask to be applied to the status bytes received.
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This parameter can be any value between 0 and 0xFFFFFFFF */
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uint32_t MatchMode; /*!< Specifies the method used for determining a match.
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This parameter can be a value of @ref OSPI_MatchMode */
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uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match.
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This parameter can be a value of @ref OSPI_AutomaticStop */
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uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases.
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This parameter can be any value between 0 and 0xFFFF */
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} OSPI_AutoPollingTypeDef;
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/**
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* @brief HAL OSPI Memory Mapped mode configuration structure definition
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*/
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typedef struct
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{
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uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select.
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This parameter can be a value of @ref OSPI_TimeOutActivation */
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uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select.
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This parameter can be any value between 0 and 0xFFFF */
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} OSPI_MemoryMappedTypeDef;
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/**
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* @brief HAL OSPI IO Manager Configuration structure definition
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*/
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typedef struct
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{
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uint32_t ClkPort; /*!< It indicates which port of the OSPI IO Manager is used for the CLK pins.
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This parameter can be a value between 1 and 8 */
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uint32_t DQSPort; /*!< It indicates which port of the OSPI IO Manager is used for the DQS pin.
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This parameter can be a value between 0 and 8, 0 means that signal not used */
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uint32_t NCSPort; /*!< It indicates which port of the OSPI IO Manager is used for the NCS pin.
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This parameter can be a value between 1 and 8 */
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uint32_t IOLowPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins.
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This parameter can be a value of @ref OSPIM_IOPort */
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uint32_t IOHighPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins.
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This parameter can be a value of @ref OSPIM_IOPort */
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#if defined (OCTOSPIM_CR_MUXEN)
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uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected
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if some signals are multiplexed in the OSPI IO Manager with the other OSPI.
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This parameter can be a value between 1 and 256 */
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#endif
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} OSPIM_CfgTypeDef;
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#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
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/**
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* @brief HAL OSPI Callback ID enumeration definition
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*/
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typedef enum
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{
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HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */
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HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */
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HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */
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HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */
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HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */
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HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */
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HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */
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HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */
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HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */
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HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */
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HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */
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HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */
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} HAL_OSPI_CallbackIDTypeDef;
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/**
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* @brief HAL OSPI Callback pointer definition
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*/
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typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
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#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup OSPI_Exported_Constants OSPI Exported Constants
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* @{
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*/
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/** @defgroup OSPI_State OSPI State
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* @{
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*/
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#define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */
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#define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */
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#define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */
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#define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */
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#define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */
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#define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */
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#define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */
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#define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */
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#define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */
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#define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */
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#define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */
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#define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */
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#define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */
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/**
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* @}
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*/
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/** @defgroup OSPI_ErrorCode OSPI Error Code
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* @{
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*/
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#define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
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#define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
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#define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
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#define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
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#define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
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#define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */
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#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
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#define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */
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#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
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/**
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* @}
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*/
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/** @defgroup OSPI_DualQuad OSPI Dual-Quad
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* @{
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*/
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#define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */
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#define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */
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/**
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* @}
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*/
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/** @defgroup OSPI_MemoryType OSPI Memory Type
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* @{
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*/
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#define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */
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#define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */
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#if !defined(STM32L4R5xx)&&!defined(STM32L4R7xx)&&!defined(STM32L4R9xx)&&!defined(STM32L4S5xx)&&!defined(STM32L4S7xx)&&!defined(STM32L4S9xx)
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#define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */
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#endif
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#define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */
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#define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */
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/**
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* @}
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*/
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/** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock
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* @{
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*/
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#define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */
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#define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */
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/**
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* @}
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*/
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/** @defgroup OSPI_ClockMode OSPI Clock Mode
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* @{
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*/
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#define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */
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#define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */
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/**
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* @}
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*/
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/** @defgroup OSPI_SampleShifting OSPI Sample Shifting
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* @{
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*/
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#define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */
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#define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */
|
|
#define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_DelayBlockBypass OSPI Delay Block Bypaas
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U) /*!< Sampling clock is delayed by the delay block */
|
|
#define HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP) /*!< Delay block is bypassed */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_OperationType OSPI Operation Type
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */
|
|
#define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */
|
|
#define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_FlashID OSPI Flash Id
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */
|
|
#define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_InstructionMode OSPI Instruction Mode
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */
|
|
#define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */
|
|
#define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */
|
|
#define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */
|
|
#define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_InstructionSize OSPI Instruction Size
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */
|
|
#define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */
|
|
#define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */
|
|
#define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */
|
|
#define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_AddressMode OSPI Address Mode
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */
|
|
#define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */
|
|
#define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */
|
|
#define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */
|
|
#define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_AddressSize OSPI Address Size
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */
|
|
#define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */
|
|
#define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */
|
|
#define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */
|
|
#define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */
|
|
#define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */
|
|
#define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */
|
|
#define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */
|
|
#define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */
|
|
#define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */
|
|
#define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */
|
|
#define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */
|
|
#define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_DataMode OSPI Data Mode
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */
|
|
#define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */
|
|
#define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */
|
|
#define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */
|
|
#define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */
|
|
#define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_DQSMode OSPI DQS Mode
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */
|
|
#define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_SIOOMode OSPI SIOO Mode
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */
|
|
#define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */
|
|
#define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */
|
|
#define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */
|
|
#define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_MatchMode OSPI Match Mode
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */
|
|
#define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_AutomaticStop OSPI Automatic Stop
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */
|
|
#define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */
|
|
#define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_Flags OSPI Flags
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */
|
|
#define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */
|
|
#define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */
|
|
#define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */
|
|
#define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */
|
|
#define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_Interrupts OSPI Interrupts
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */
|
|
#define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */
|
|
#define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */
|
|
#define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */
|
|
#define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPI_Timeout_definition OSPI Timeout definition
|
|
* @{
|
|
*/
|
|
#define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup OSPIM_IOPort OSPI IO Manager IO Port
|
|
* @{
|
|
*/
|
|
#define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U) /*!< IOs not used */
|
|
#define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */
|
|
#define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */
|
|
#define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */
|
|
#define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U)) /*!< Port 2 - IO[7:4] */
|
|
/**
|
|
* @}
|
|
*/
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Exported macros -----------------------------------------------------------*/
|
|
/** @defgroup OSPI_Exported_Macros OSPI Exported Macros
|
|
* @{
|
|
*/
|
|
/** @brief Reset OSPI handle state.
|
|
* @param __HANDLE__ specifies the OSPI Handle.
|
|
* @retval None
|
|
*/
|
|
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
|
|
#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
|
|
(__HANDLE__)->State = HAL_OSPI_STATE_RESET; \
|
|
(__HANDLE__)->MspInitCallback = NULL; \
|
|
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
} while(0)
|
|
#else
|
|
#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET)
|
|
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
|
|
|
|
/** @brief Enable the OSPI peripheral.
|
|
* @param __HANDLE__ specifies the OSPI Handle.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
|
|
|
|
/** @brief Disable the OSPI peripheral.
|
|
* @param __HANDLE__ specifies the OSPI Handle.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
|
|
|
|
/** @brief Enable the specified OSPI interrupt.
|
|
* @param __HANDLE__ specifies the OSPI Handle.
|
|
* @param __INTERRUPT__ specifies the OSPI interrupt source to enable.
|
|
* This parameter can be one of the following values:
|
|
* @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
|
|
* @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
|
|
* @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
|
|
* @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
|
|
* @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
|
|
* @retval None
|
|
*/
|
|
#define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
|
|
|
|
|
|
/** @brief Disable the specified OSPI interrupt.
|
|
* @param __HANDLE__ specifies the OSPI Handle.
|
|
* @param __INTERRUPT__ specifies the OSPI interrupt source to disable.
|
|
* This parameter can be one of the following values:
|
|
* @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
|
|
* @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
|
|
* @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
|
|
* @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
|
|
* @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
|
|
* @retval None
|
|
*/
|
|
#define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
|
|
|
|
/** @brief Check whether the specified OSPI interrupt source is enabled or not.
|
|
* @param __HANDLE__ specifies the OSPI Handle.
|
|
* @param __INTERRUPT__ specifies the OSPI interrupt source to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
|
|
* @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
|
|
* @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
|
|
* @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
|
|
* @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
|
|
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
|
*/
|
|
#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\
|
|
== (__INTERRUPT__))
|
|
|
|
/**
|
|
* @brief Check whether the selected OSPI flag is set or not.
|
|
* @param __HANDLE__ specifies the OSPI Handle.
|
|
* @param __FLAG__ specifies the OSPI flag to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag
|
|
* @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag
|
|
* @arg HAL_OSPI_FLAG_SM: OSPI Status match flag
|
|
* @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag
|
|
* @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag
|
|
* @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag
|
|
* @retval None
|
|
*/
|
|
#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \
|
|
!= 0U) ? SET : RESET)
|
|
|
|
/** @brief Clears the specified OSPI's flag status.
|
|
* @param __HANDLE__ specifies the OSPI Handle.
|
|
* @param __FLAG__ specifies the OSPI clear register flag that needs to be set
|
|
* This parameter can be one of the following values:
|
|
* @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag
|
|
* @arg HAL_OSPI_FLAG_SM: OSPI Status match flag
|
|
* @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag
|
|
* @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag
|
|
* @retval None
|
|
*/
|
|
#define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Exported functions --------------------------------------------------------*/
|
|
/** @addtogroup OSPI_Exported_Functions
|
|
* @{
|
|
*/
|
|
|
|
/* Initialization/de-initialization functions ********************************/
|
|
/** @addtogroup OSPI_Exported_Functions_Group1
|
|
* @{
|
|
*/
|
|
HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi);
|
|
void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi);
|
|
HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi);
|
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void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi);
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/**
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* @}
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*/
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/* IO operation functions *****************************************************/
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/** @addtogroup OSPI_Exported_Functions_Group2
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* @{
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*/
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/* OSPI IRQ handler function */
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void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi);
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/* OSPI command configuration functions */
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HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
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HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
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HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout);
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HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout);
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/* OSPI indirect mode functions */
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HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
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HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
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HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData);
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HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData);
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HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData);
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HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData);
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/* OSPI status flag polling mode functions */
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HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
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HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
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/* OSPI memory-mapped mode functions */
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HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
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/* Callback functions in non-blocking modes ***********************************/
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void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi);
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void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi);
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void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi);
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/* OSPI indirect mode functions */
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void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi);
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void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi);
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void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi);
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void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi);
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void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi);
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/* OSPI status flag polling mode functions */
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void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi);
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/* OSPI memory-mapped mode functions */
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void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi);
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#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
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/* OSPI callback registering/unregistering */
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HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID,
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pOSPI_CallbackTypeDef pCallback);
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HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID);
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#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
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/**
|
|
* @}
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*/
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/* Peripheral Control and State functions ************************************/
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/** @addtogroup OSPI_Exported_Functions_Group3
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* @{
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|
*/
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HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi);
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HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi);
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HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold);
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uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi);
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HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout);
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uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi);
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uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi);
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|
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/**
|
|
* @}
|
|
*/
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/* OSPI IO Manager configuration function ************************************/
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/** @addtogroup OSPI_Exported_Functions_Group4
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* @{
|
|
*/
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HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout);
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|
|
|
/**
|
|
* @}
|
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*/
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/**
|
|
* @}
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*/
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/* End of exported functions -------------------------------------------------*/
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|
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/* Private macros ------------------------------------------------------------*/
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/**
|
|
@cond 0
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*/
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#define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U))
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#define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \
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((MODE) == HAL_OSPI_DUALQUAD_ENABLE))
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|
|
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
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#define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \
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((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \
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((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \
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((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS))
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|
#else
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|
#define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \
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((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \
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|
((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \
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|
((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \
|
|
((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS))
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|
#endif
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|
|
|
#define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U))
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|
|
|
#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U))
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|
|
|
#define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \
|
|
((CLK) == HAL_OSPI_FREERUNCLK_ENABLE))
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|
|
|
#define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \
|
|
((MODE) == HAL_OSPI_CLOCK_MODE_3))
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|
|
|
#define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U))
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|
|
|
#define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \
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|
((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE))
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|
|
|
#define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \
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|
((CYCLE) == HAL_OSPI_DHQC_ENABLE))
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|
|
|
#define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \
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|
((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \
|
|
((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG))
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|
|
|
#define IS_OSPI_FLASH_ID(FLASHID) (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \
|
|
((FLASHID) == HAL_OSPI_FLASH_ID_2))
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|
|
|
#define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \
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|
((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \
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|
((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \
|
|
((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \
|
|
((MODE) == HAL_OSPI_INSTRUCTION_8_LINES))
|
|
|
|
#define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \
|
|
((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \
|
|
((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \
|
|
((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS))
|
|
|
|
#define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \
|
|
((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
|
|
|
|
#define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \
|
|
((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \
|
|
((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \
|
|
((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \
|
|
((MODE) == HAL_OSPI_ADDRESS_8_LINES))
|
|
|
|
#define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \
|
|
((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \
|
|
((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \
|
|
((SIZE) == HAL_OSPI_ADDRESS_32_BITS))
|
|
|
|
#define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \
|
|
((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE))
|
|
|
|
#define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \
|
|
((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \
|
|
((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \
|
|
((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \
|
|
((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES))
|
|
|
|
#define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \
|
|
((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \
|
|
((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \
|
|
((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS))
|
|
|
|
#define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \
|
|
((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE))
|
|
|
|
#define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \
|
|
((MODE) == HAL_OSPI_DATA_1_LINE) || \
|
|
((MODE) == HAL_OSPI_DATA_2_LINES) || \
|
|
((MODE) == HAL_OSPI_DATA_4_LINES) || \
|
|
((MODE) == HAL_OSPI_DATA_8_LINES))
|
|
|
|
#define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U)
|
|
|
|
#define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \
|
|
((MODE) == HAL_OSPI_DATA_DTR_ENABLE))
|
|
|
|
#define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U)
|
|
|
|
#define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \
|
|
((MODE) == HAL_OSPI_DQS_ENABLE))
|
|
|
|
#define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \
|
|
((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD))
|
|
|
|
#define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U)
|
|
|
|
#define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U)
|
|
|
|
#define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \
|
|
((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE))
|
|
|
|
#define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \
|
|
((MODE) == HAL_OSPI_FIXED_LATENCY))
|
|
|
|
#define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \
|
|
((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE))
|
|
|
|
#define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \
|
|
((MODE) == HAL_OSPI_MATCH_MODE_OR))
|
|
|
|
#define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \
|
|
((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE))
|
|
|
|
#define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU)
|
|
|
|
#define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
|
|
|
|
#define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \
|
|
((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE))
|
|
|
|
#define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
|
|
|
|
#define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U)
|
|
|
|
#define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \
|
|
((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))
|
|
#if defined (OCTOSPI_DCR3_MAXTRAN)
|
|
|
|
#define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U)
|
|
#endif
|
|
|
|
#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 2U))
|
|
|
|
#define IS_OSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 2U)
|
|
|
|
#define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_NONE) || \
|
|
((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \
|
|
((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \
|
|
((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \
|
|
((PORT) == HAL_OSPIM_IOPORT_2_HIGH))
|
|
|
|
#if defined (OCTOSPIM_CR_MUXEN)
|
|
#define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U))
|
|
#endif /*(OCTOSPIM_CR_MUXEN)*/
|
|
/**
|
|
@endcond
|
|
*/
|
|
|
|
/* End of private macros -----------------------------------------------------*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* STM32L4xx_HAL_OSPI_H */
|