286 lines
12 KiB
NASM
286 lines
12 KiB
NASM
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;********************************************************************************************************
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; uC/CPU
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; CPU CONFIGURATION & PORT LAYER
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;
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; (c) Copyright 2004-2011; Micrium, Inc.; Weston, FL
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;
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; All rights reserved. Protected by international copyright laws.
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;
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; uC/CPU is provided in source form to registered licensees ONLY. It is
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; illegal to distribute this source code to any third party unless you receive
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; written permission by an authorized Micrium representative. Knowledge of
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; the source code may NOT be used to develop a similar product.
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;
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; Please help us continue to provide the Embedded community with the finest
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; software available. Your honesty is greatly appreciated.
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;
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; You can contact us at www.micrium.com.
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;********************************************************************************************************
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;********************************************************************************************************
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;
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; CPU PORT FILE
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;
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; ARM-Cortex-M4
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; IAR C Compiler
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;
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; Filename : cpu_a.asm
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; Version : V1.29.01.00
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; Programmer(s) : JJL
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;********************************************************************************************************
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;********************************************************************************************************
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; PUBLIC FUNCTIONS
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;********************************************************************************************************
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PUBLIC CPU_IntDis
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PUBLIC CPU_IntEn
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PUBLIC CPU_SR_Save
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PUBLIC CPU_SR_Restore
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PUBLIC CPU_WaitForInt
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PUBLIC CPU_WaitForExcept
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PUBLIC CPU_CntLeadZeros
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PUBLIC CPU_CntTrailZeros
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PUBLIC CPU_RevBits
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;********************************************************************************************************
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; CODE GENERATION DIRECTIVES
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;********************************************************************************************************
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RSEG CODE:CODE:NOROOT(2)
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THUMB
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;$PAGE
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;********************************************************************************************************
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; DISABLE and ENABLE INTERRUPTS
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;
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; Description: Disable/Enable interrupts.
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;
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; Prototypes : void CPU_IntDis(void);
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; void CPU_IntEn (void);
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;********************************************************************************************************
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CPU_IntDis
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CPSID I
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BX LR
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CPU_IntEn
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CPSIE I
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BX LR
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;********************************************************************************************************
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; CRITICAL SECTION FUNCTIONS
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;
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; Description : Disable/Enable interrupts by preserving the state of interrupts. Generally speaking, the
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; state of the interrupt disable flag is stored in the local variable 'cpu_sr' & interrupts
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; are then disabled ('cpu_sr' is allocated in all functions that need to disable interrupts).
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; The previous interrupt state is restored by copying 'cpu_sr' into the CPU's status register.
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;
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; Prototypes : CPU_SR CPU_SR_Save (void);
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; void CPU_SR_Restore(CPU_SR cpu_sr);
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;
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; Note(s) : (1) These functions are used in general like this :
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;
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; void Task (void *p_arg)
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; {
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; CPU_SR_ALLOC(); /* Allocate storage for CPU status register */
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; :
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; :
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; CPU_CRITICAL_ENTER(); /* cpu_sr = CPU_SR_Save(); */
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; :
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; :
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; CPU_CRITICAL_EXIT(); /* CPU_SR_Restore(cpu_sr); */
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; :
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; }
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;********************************************************************************************************
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CPU_SR_Save
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MRS R0, PRIMASK ; Set prio int mask to mask all (except faults)
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CPSID I
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BX LR
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CPU_SR_Restore ; See Note #2.
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MSR PRIMASK, R0
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BX LR
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;$PAGE
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;********************************************************************************************************
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; WAIT FOR INTERRUPT
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;
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; Description : Enters sleep state, which will be exited when an interrupt is received.
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;
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; Prototypes : void CPU_WaitForInt (void)
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;
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; Argument(s) : none.
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;********************************************************************************************************
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CPU_WaitForInt:
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WFI ; Wait for interrupt
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BX LR
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;********************************************************************************************************
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; WAIT FOR EXCEPTION
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;
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; Description : Enters sleep state, which will be exited when an exception is received.
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;
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; Prototypes : void CPU_WaitForExcept (void)
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;
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; Argument(s) : none.
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;********************************************************************************************************
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CPU_WaitForExcept:
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WFE ; Wait for exception
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BX LR
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;$PAGE
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;********************************************************************************************************
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; CPU_CntLeadZeros()
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; COUNT LEADING ZEROS
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;
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; Description : Counts the number of contiguous, most-significant, leading zero bits before the
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; first binary one bit in a data value.
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;
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; Prototype : CPU_DATA CPU_CntLeadZeros(CPU_DATA val);
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;
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; Argument(s) : val Data value to count leading zero bits.
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;
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; Return(s) : Number of contiguous, most-significant, leading zero bits in 'val'.
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;
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; Caller(s) : Application.
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;
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; This function is an INTERNAL CPU module function but MAY be called by application
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; function(s).
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;
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; Note(s) : (1) (a) Supports 32-bit data value size as configured by 'CPU_DATA' (see 'cpu.h
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; CPU WORD CONFIGURATION Note #1').
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;
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; (b) For 32-bit values :
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;
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; b31 b30 b29 ... b04 b03 b02 b01 b00 # Leading Zeros
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; --- --- --- --- --- --- --- --- ---------------
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; 1 x x x x x x x 0
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; 0 1 x x x x x x 1
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; 0 0 1 x x x x x 2
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; : : : : : : : : :
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; : : : : : : : : :
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; 0 0 0 1 x x x x 27
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; 0 0 0 0 1 x x x 28
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; 0 0 0 0 0 1 x x 29
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; 0 0 0 0 0 0 1 x 30
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; 0 0 0 0 0 0 0 1 31
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; 0 0 0 0 0 0 0 0 32
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;
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;
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; (2) MUST be defined in 'cpu_a.asm' (or 'cpu_c.c') if CPU_CFG_LEAD_ZEROS_ASM_PRESENT is
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; #define'd in 'cpu_cfg.h' or 'cpu.h'.
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;********************************************************************************************************
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CPU_CntLeadZeros:
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CLZ R0, R0 ; Count leading zeros
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BX LR
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;$PAGE
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;********************************************************************************************************
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; CPU_CntTrailZeros()
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; COUNT TRAILING ZEROS
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;
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; Description : Counts the number of contiguous, least-significant, trailing zero bits before the
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; first binary one bit in a data value.
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;
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; Prototype : CPU_DATA CPU_CntTrailZeros(CPU_DATA val);
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;
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; Argument(s) : val Data value to count trailing zero bits.
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;
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; Return(s) : Number of contiguous, least-significant, trailing zero bits in 'val'.
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;
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; Caller(s) : Application.
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;
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; This function is an INTERNAL CPU module function but MAY be called by application
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; function(s).
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;
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; Note(s) : (1) (a) Supports 32-bit data value size as configured by 'CPU_DATA' (see 'cpu.h
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; CPU WORD CONFIGURATION Note #1').
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;
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; (b) For 32-bit values :
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;
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; b31 b30 b29 b28 b27 ... b02 b01 b00 # Trailing Zeros
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; --- --- --- --- --- --- --- --- ----------------
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; x x x x x x x 1 0
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; x x x x x x 1 0 1
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; x x x x x 1 0 0 2
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; : : : : : : : : :
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; : : : : : : : : :
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; x x x x 1 0 0 0 27
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; x x x 1 0 0 0 0 28
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; x x 1 0 0 0 0 0 29
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; x 1 0 0 0 0 0 0 30
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; 1 0 0 0 0 0 0 0 31
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; 0 0 0 0 0 0 0 0 32
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;
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;
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; (2) MUST be defined in 'cpu_a.asm' (or 'cpu_c.c') if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT is
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; #define'd in 'cpu_cfg.h' or 'cpu.h'.
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;********************************************************************************************************
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CPU_CntTrailZeros:
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RBIT R0, R0 ; Reverse bits
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CLZ R0, R0 ; Count trailing zeros
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BX LR
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;$PAGE
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;********************************************************************************************************
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; CPU_RevBits()
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; REVERSE BITS
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;
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; Description : Reverses the bits in a data value.
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;
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; Prototypes : CPU_DATA CPU_RevBits(CPU_DATA val);
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;
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; Argument(s) : val Data value to reverse bits.
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;
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; Return(s) : Value with all bits in 'val' reversed (see Note #1).
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;
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; Caller(s) : Application.
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;
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; This function is an INTERNAL CPU module function but MAY be called by application function(s).
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;
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; Note(s) : (1) The final, reversed data value for 'val' is such that :
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;
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; 'val's final bit 0 = 'val's original bit N
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; 'val's final bit 1 = 'val's original bit (N - 1)
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; 'val's final bit 2 = 'val's original bit (N - 2)
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;
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; ... ...
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;
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; 'val's final bit (N - 2) = 'val's original bit 2
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; 'val's final bit (N - 1) = 'val's original bit 1
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; 'val's final bit N = 'val's original bit 0
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;********************************************************************************************************
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CPU_RevBits:
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RBIT R0, R0 ; Reverse bits
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BX LR
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;$PAGE
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;********************************************************************************************************
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; CPU ASSEMBLY PORT FILE END
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;********************************************************************************************************
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END
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