756 lines
30 KiB
C
756 lines
30 KiB
C
/*
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*********************************************************************************************************
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* uC/CPU
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* CPU CONFIGURATION & PORT LAYER
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*
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* (c) Copyright 2004-2011; Micrium, Inc.; Weston, FL
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*
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* All rights reserved. Protected by international copyright laws.
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*
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* uC/CPU is provided in source form to registered licensees ONLY. It is
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* illegal to distribute this source code to any third party unless you receive
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* written permission by an authorized Micrium representative. Knowledge of
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* the source code may NOT be used to develop a similar product.
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*
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* Please help us continue to provide the Embedded community with the finest
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* software available. Your honesty is greatly appreciated.
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*
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* You can contact us at www.micrium.com.
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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*
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* CPU PORT FILE
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*
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* ARM-Cortex-M4
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* IAR C Compiler
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*
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* Filename : cpu_c.c
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* Version : V1.29.01.00
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* Programmer(s) : JJL
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* BAN
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* INCLUDE FILES
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*********************************************************************************************************
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*/
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#define MICRIUM_SOURCE
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#include <cpu.h>
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#include <cpu_core.h>
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#include <lib_def.h>
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/*$PAGE*/
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/*
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*********************************************************************************************************
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* LOCAL DEFINES
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*********************************************************************************************************
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*/
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#define CPU_INT_SRC_POS_MAX ((((CPU_REG_NVIC_NVIC + 1) & 0x1F) * 32) + 16)
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#define CPU_BIT_BAND_SRAM_REG_LO 0x20000000
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#define CPU_BIT_BAND_SRAM_REG_HI 0x200FFFFF
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#define CPU_BIT_BAND_SRAM_BASE 0x22000000
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#define CPU_BIT_BAND_PERIPH_REG_LO 0x40000000
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#define CPU_BIT_BAND_PERIPH_REG_HI 0x400FFFFF
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#define CPU_BIT_BAND_PERIPH_BASE 0x42000000
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/*
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*********************************************************************************************************
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* LOCAL CONSTANTS
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* LOCAL DATA TYPES
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* LOCAL TABLES
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* LOCAL GLOBAL VARIABLES
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* LOCAL FUNCTION PROTOTYPES
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* LOCAL CONFIGURATION ERRORS
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*********************************************************************************************************
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*/
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/*$PAGE*/
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/*
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*********************************************************************************************************
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* CPU_BitBandClr()
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*
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* Description : Clear bit in bit-band region.
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*
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* Argument(s) : addr Byte address in memory space.
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*
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* bit_nbr Bit number in byte.
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*
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* Return(s) : none.
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*
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* Caller(s) : Application.
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*
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* Note(s) : none.
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*********************************************************************************************************
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*/
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void CPU_BitBandClr (CPU_ADDR addr,
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CPU_INT08U bit_nbr)
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{
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CPU_ADDR bit_word_off;
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CPU_ADDR bit_word_addr;
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if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
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(addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
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bit_word_off = ((addr - CPU_BIT_BAND_SRAM_REG_LO ) * 32) + (bit_nbr * 4);
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bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
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*(volatile CPU_INT32U *)(bit_word_addr) = 0;
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} else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
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(addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
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bit_word_off = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
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bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
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*(volatile CPU_INT32U *)(bit_word_addr) = 0;
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}
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}
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/*$PAGE*/
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/*
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*********************************************************************************************************
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* CPU_BitBandSet()
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*
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* Description : Set bit in bit-band region.
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*
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* Argument(s) : addr Byte address in memory space.
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*
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* bit_nbr Bit number in byte.
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*
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* Return(s) : none.
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*
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* Caller(s) : Application.
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*
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* Note(s) : none.
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*********************************************************************************************************
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*/
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void CPU_BitBandSet (CPU_ADDR addr,
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CPU_INT08U bit_nbr)
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{
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CPU_ADDR bit_word_off;
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CPU_ADDR bit_word_addr;
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if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
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(addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
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bit_word_off = ((addr - CPU_BIT_BAND_SRAM_REG_LO ) * 32) + (bit_nbr * 4);
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bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
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*(volatile CPU_INT32U *)(bit_word_addr) = 1;
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} else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
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(addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
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bit_word_off = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
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bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
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*(volatile CPU_INT32U *)(bit_word_addr) = 1;
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}
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}
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/*$PAGE*/
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/*
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*********************************************************************************************************
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* CPU_IntSrcDis()
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*
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* Description : Disable an interrupt source.
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*
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* Argument(s) : pos Position of interrupt vector in interrupt table :
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*
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* 0 Invalid (see Note #1a).
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* 1 Invalid (see Note #1b).
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* 2 Non-maskable interrupt.
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* 3 Hard Fault.
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* 4 Memory Management.
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* 5 Bus Fault.
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* 6 Usage Fault.
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* 7-10 Reserved.
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* 11 SVCall
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* 12 Debug monitor.
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* 13 Reserved
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* 14 PendSV.
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* 15 SysTick.
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* 16+ External Interrupt.
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*
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* Return(s) : none.
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*
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* Caller(s) : Application.
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*
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* Note(s) : (1) Several table positions do not contain interrupt sources :
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*
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* (a) Position 0 contains the stack pointer.
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* (b) Positions 7-10, 13 are reserved.
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*
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* (2) Several interrupts cannot be disabled/enabled :
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*
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* (a) Reset.
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* (b) NMI.
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* (c) Hard fault.
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* (d) SVCall.
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* (e) Debug monitor.
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* (f) PendSV.
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*
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* (3) The maximum Cortex-M3 table position is 256. A particular Cortex-M3 may have fewer
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* than 240 external exceptions and, consequently, fewer than 256 table positions.
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* This function assumes that the specified table position is valid if the interrupt
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* controller type register's INTLINESNUM field is large enough so that the position
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* COULD be valid.
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*********************************************************************************************************
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*/
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/*$PAGE*/
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void CPU_IntSrcDis (CPU_INT08U pos)
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{
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CPU_INT08U group;
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CPU_INT08U pos_max;
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CPU_INT08U nbr;
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CPU_SR_ALLOC();
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switch (pos) {
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case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
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case CPU_INT_RSVD_07:
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case CPU_INT_RSVD_08:
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case CPU_INT_RSVD_09:
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case CPU_INT_RSVD_10:
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case CPU_INT_RSVD_13:
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break;
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/* ----------------- SYSTEM EXCEPTIONS ---------------- */
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case CPU_INT_RESET: /* Reset (see Note #2). */
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case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
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case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
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case CPU_INT_SVCALL: /* SVCall (see Note #2). */
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case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
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case CPU_INT_PENDSV: /* PendSV (see Note #2). */
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break;
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case CPU_INT_MEM: /* Memory management. */
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CPU_CRITICAL_ENTER();
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CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_MEMFAULTENA;
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CPU_CRITICAL_EXIT();
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break;
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case CPU_INT_BUSFAULT: /* Bus fault. */
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CPU_CRITICAL_ENTER();
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CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_BUSFAULTENA;
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CPU_CRITICAL_EXIT();
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break;
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case CPU_INT_USAGEFAULT: /* Usage fault. */
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CPU_CRITICAL_ENTER();
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CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_USGFAULTENA;
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CPU_CRITICAL_EXIT();
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break;
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case CPU_INT_SYSTICK: /* SysTick. */
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CPU_CRITICAL_ENTER();
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CPU_REG_NVIC_ST_CTRL &= ~CPU_REG_NVIC_ST_CTRL_ENABLE;
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CPU_CRITICAL_EXIT();
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break;
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/* ---------------- EXTERNAL INTERRUPT ---------------- */
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default:
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pos_max = CPU_INT_SRC_POS_MAX;
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if (pos < pos_max) { /* See Note #3. */
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group = (pos - 16) / 32;
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nbr = (pos - 16) % 32;
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CPU_CRITICAL_ENTER();
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CPU_REG_NVIC_CLREN(group) = DEF_BIT(nbr);
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CPU_CRITICAL_EXIT();
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}
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break;
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}
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}
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/*$PAGE*/
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/*
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*********************************************************************************************************
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* CPU_IntSrcEn()
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*
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* Description : Enable an interrupt source.
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*
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* Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
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*
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* Return(s) : none.
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*
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* Caller(s) : Application.
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*
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* Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
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*
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* (2) See 'CPU_IntSrcDis() Note #2'.
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*
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* (3) See 'CPU_IntSrcDis() Note #3'.
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*********************************************************************************************************
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*/
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void CPU_IntSrcEn (CPU_INT08U pos)
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{
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CPU_INT08U group;
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CPU_INT08U nbr;
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CPU_INT08U pos_max;
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CPU_SR_ALLOC();
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switch (pos) {
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case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
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case CPU_INT_RSVD_07:
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case CPU_INT_RSVD_08:
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case CPU_INT_RSVD_09:
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case CPU_INT_RSVD_10:
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case CPU_INT_RSVD_13:
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break;
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/* ----------------- SYSTEM EXCEPTIONS ---------------- */
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case CPU_INT_RESET: /* Reset (see Note #2). */
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case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
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case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
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case CPU_INT_SVCALL: /* SVCall (see Note #2). */
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case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
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case CPU_INT_PENDSV: /* PendSV (see Note #2). */
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break;
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case CPU_INT_MEM: /* Memory management. */
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CPU_CRITICAL_ENTER();
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CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_MEMFAULTENA;
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CPU_CRITICAL_EXIT();
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break;
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case CPU_INT_BUSFAULT: /* Bus fault. */
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CPU_CRITICAL_ENTER();
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CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_BUSFAULTENA;
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CPU_CRITICAL_EXIT();
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break;
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case CPU_INT_USAGEFAULT: /* Usage fault. */
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CPU_CRITICAL_ENTER();
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CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_USGFAULTENA;
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CPU_CRITICAL_EXIT();
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break;
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case CPU_INT_SYSTICK: /* SysTick. */
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CPU_CRITICAL_ENTER();
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CPU_REG_NVIC_ST_CTRL |= CPU_REG_NVIC_ST_CTRL_ENABLE;
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CPU_CRITICAL_EXIT();
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break;
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/* ---------------- EXTERNAL INTERRUPT ---------------- */
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default:
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pos_max = CPU_INT_SRC_POS_MAX;
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if (pos < pos_max) { /* See Note #3. */
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group = (pos - 16) / 32;
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nbr = (pos - 16) % 32;
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CPU_CRITICAL_ENTER();
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CPU_REG_NVIC_SETEN(group) = DEF_BIT(nbr);
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CPU_CRITICAL_EXIT();
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}
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break;
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}
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}
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/*$PAGE*/
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/*
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*********************************************************************************************************
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* CPU_IntSrcPendClr()
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*
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* Description : Clear a pending interrupt.
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*
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* Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
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*
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* Return(s) : none.
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*
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* Caller(s) : Application.
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*
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* Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
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*
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* (2) The pending status of several interrupts cannot be clear/set :
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*
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* (a) Reset.
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* (b) NMI.
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* (c) Hard fault.
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* (d) Memory Managment.
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* (e) Bus Fault.
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* (f) Usage Fault.
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* (g) SVCall.
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* (h) Debug monitor.
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* (i) PendSV.
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* (j) Systick
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*
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* (3) See 'CPU_IntSrcDis() Note #3'.
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*********************************************************************************************************
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*/
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void CPU_IntSrcPendClr (CPU_INT08U pos)
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{
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CPU_INT08U group;
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CPU_INT08U nbr;
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CPU_INT08U pos_max;
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CPU_SR_ALLOC();
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switch (pos) {
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case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
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case CPU_INT_RSVD_07:
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case CPU_INT_RSVD_08:
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case CPU_INT_RSVD_09:
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case CPU_INT_RSVD_10:
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case CPU_INT_RSVD_13:
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break;
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/* ----------------- SYSTEM EXCEPTIONS ---------------- */
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case CPU_INT_RESET: /* Reset (see Note #2). */
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case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
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case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
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case CPU_INT_MEM: /* Memory management (see Note #2). */
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case CPU_INT_SVCALL: /* SVCall (see Note #2). */
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case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
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case CPU_INT_PENDSV: /* PendSV (see Note #2). */
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case CPU_INT_BUSFAULT: /* Bus fault. */
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case CPU_INT_USAGEFAULT: /* Usage fault. */
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case CPU_INT_SYSTICK: /* SysTick. */
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break;
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/* ---------------- EXTERNAL INTERRUPT ---------------- */
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default:
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pos_max = CPU_INT_SRC_POS_MAX;
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if (pos < pos_max) { /* See Note #3. */
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group = (pos - 16) / 32;
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nbr = (pos - 16) % 32;
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CPU_CRITICAL_ENTER();
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CPU_REG_NVIC_CLRPEND(group) = DEF_BIT(nbr);
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CPU_CRITICAL_EXIT();
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}
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break;
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}
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}
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/*$PAGE*/
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/*
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*********************************************************************************************************
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* CPU_IntSrcPrioSet()
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*
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* Description : Set priority of an interrupt source.
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*
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* Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
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*
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* prio Priority. Use a lower priority number for a higher priority.
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*
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* Return(s) : none.
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*
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* Caller(s) : Application.
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*
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* Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
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*
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* (2) Several interrupts priorities CANNOT be set :
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*
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* (a) Reset (always -3).
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* (b) NMI (always -2).
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* (c) Hard fault (always -1).
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*
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* (3) See 'CPU_IntSrcDis() Note #3'.
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*********************************************************************************************************
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*/
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void CPU_IntSrcPrioSet (CPU_INT08U pos,
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CPU_INT08U prio)
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{
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CPU_INT08U group;
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CPU_INT08U nbr;
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CPU_INT08U pos_max;
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CPU_INT32U prio_32;
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CPU_INT32U temp;
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CPU_SR_ALLOC();
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prio_32 = CPU_RevBits((CPU_INT08U)prio);
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prio = (CPU_INT08U)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
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switch (pos) {
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case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
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case CPU_INT_RSVD_07:
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case CPU_INT_RSVD_08:
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case CPU_INT_RSVD_09:
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case CPU_INT_RSVD_10:
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case CPU_INT_RSVD_13:
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break;
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/* ----------------- SYSTEM EXCEPTIONS ---------------- */
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case CPU_INT_RESET: /* Reset (see Note #2). */
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case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
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case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
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break;
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case CPU_INT_MEM: /* Memory management. */
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CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_SHPRI1;
|
||
temp &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
|
||
temp |= (prio << (0 * DEF_OCTET_NBR_BITS));
|
||
CPU_REG_NVIC_SHPRI1 = temp;
|
||
CPU_CRITICAL_EXIT();
|
||
break;
|
||
|
||
case CPU_INT_BUSFAULT: /* Bus fault. */
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_SHPRI1;
|
||
temp &= ~(DEF_OCTET_MASK << (1 * DEF_OCTET_NBR_BITS));
|
||
temp |= (prio << (1 * DEF_OCTET_NBR_BITS));
|
||
CPU_REG_NVIC_SHPRI1 = temp;
|
||
CPU_CRITICAL_EXIT();
|
||
break;
|
||
|
||
case CPU_INT_USAGEFAULT: /* Usage fault. */
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_SHPRI1;
|
||
temp &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
|
||
temp |= (prio << (2 * DEF_OCTET_NBR_BITS));
|
||
CPU_REG_NVIC_SHPRI1 = temp;
|
||
CPU_CRITICAL_EXIT();
|
||
break;
|
||
|
||
case CPU_INT_SVCALL: /* SVCall. */
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_SHPRI2;
|
||
temp &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
|
||
temp |= (prio << (3 * DEF_OCTET_NBR_BITS));
|
||
CPU_REG_NVIC_SHPRI2 = temp;
|
||
CPU_CRITICAL_EXIT();
|
||
break;
|
||
|
||
case CPU_INT_DBGMON: /* Debug monitor. */
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_SHPRI3;
|
||
temp &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
|
||
temp |= (prio << (0 * DEF_OCTET_NBR_BITS));
|
||
CPU_REG_NVIC_SHPRI3 = temp;
|
||
CPU_CRITICAL_EXIT();
|
||
break;
|
||
|
||
case CPU_INT_PENDSV: /* PendSV. */
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_SHPRI3;
|
||
temp &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
|
||
temp |= (prio << (2 * DEF_OCTET_NBR_BITS));
|
||
CPU_REG_NVIC_SHPRI3 = temp;
|
||
CPU_CRITICAL_EXIT();
|
||
break;
|
||
|
||
case CPU_INT_SYSTICK: /* SysTick. */
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_SHPRI3;
|
||
temp &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
|
||
temp |= (prio << (3 * DEF_OCTET_NBR_BITS));
|
||
CPU_REG_NVIC_SHPRI3 = temp;
|
||
CPU_CRITICAL_EXIT();
|
||
break;
|
||
|
||
|
||
/* ---------------- EXTERNAL INTERRUPT ---------------- */
|
||
default:
|
||
pos_max = CPU_INT_SRC_POS_MAX;
|
||
if (pos < pos_max) { /* See Note #3. */
|
||
group = (pos - 16) / 4;
|
||
nbr = (pos - 16) % 4;
|
||
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_PRIO(group);
|
||
temp &= ~(DEF_OCTET_MASK << (nbr * DEF_OCTET_NBR_BITS));
|
||
temp |= (prio << (nbr * DEF_OCTET_NBR_BITS));
|
||
CPU_REG_NVIC_PRIO(group) = temp;
|
||
CPU_CRITICAL_EXIT();
|
||
}
|
||
break;
|
||
}
|
||
}
|
||
|
||
|
||
/*$PAGE*/
|
||
/*
|
||
*********************************************************************************************************
|
||
* CPU_IntSrcPrioGet()
|
||
*
|
||
* Description : Get priority of an interrupt source.
|
||
*
|
||
* Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
|
||
*
|
||
* Return(s) : Priority of interrupt source. If the interrupt source specified is invalid, then
|
||
* DEF_INT_16S_MIN_VAL is returned.
|
||
*
|
||
* Caller(s) : Application.
|
||
*
|
||
* Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
|
||
*
|
||
* (2) See 'CPU_IntSrcPrioSet() Note #2'.
|
||
*
|
||
* (3) See 'CPU_IntSrcDis() Note #3'.
|
||
*********************************************************************************************************
|
||
*/
|
||
|
||
CPU_INT16S CPU_IntSrcPrioGet (CPU_INT08U pos)
|
||
{
|
||
CPU_INT08U group;
|
||
CPU_INT08U nbr;
|
||
CPU_INT08U pos_max;
|
||
CPU_INT16S prio;
|
||
CPU_INT32U prio_32;
|
||
CPU_INT32U temp;
|
||
CPU_SR_ALLOC();
|
||
|
||
|
||
switch (pos) {
|
||
case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
|
||
case CPU_INT_RSVD_07:
|
||
case CPU_INT_RSVD_08:
|
||
case CPU_INT_RSVD_09:
|
||
case CPU_INT_RSVD_10:
|
||
case CPU_INT_RSVD_13:
|
||
prio = DEF_INT_16S_MIN_VAL;
|
||
break;
|
||
|
||
|
||
/* ----------------- SYSTEM EXCEPTIONS ---------------- */
|
||
case CPU_INT_RESET: /* Reset (see Note #2). */
|
||
prio = -3;
|
||
break;
|
||
|
||
case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
|
||
prio = -2;
|
||
break;
|
||
|
||
case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
|
||
prio = -1;
|
||
break;
|
||
|
||
|
||
case CPU_INT_MEM: /* Memory management. */
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_SHPRI1;
|
||
prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
|
||
CPU_CRITICAL_EXIT();
|
||
break;
|
||
|
||
|
||
case CPU_INT_BUSFAULT: /* Bus fault. */
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_SHPRI1;
|
||
prio = (temp >> (1 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
|
||
CPU_CRITICAL_EXIT();
|
||
break;
|
||
|
||
|
||
case CPU_INT_USAGEFAULT: /* Usage fault. */
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_SHPRI1;
|
||
prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
|
||
break;
|
||
|
||
case CPU_INT_SVCALL: /* SVCall. */
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_SHPRI2;
|
||
prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
|
||
CPU_CRITICAL_EXIT();
|
||
break;
|
||
|
||
case CPU_INT_DBGMON: /* Debug monitor. */
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_SHPRI3;
|
||
prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
|
||
CPU_CRITICAL_EXIT();
|
||
break;
|
||
|
||
case CPU_INT_PENDSV: /* PendSV. */
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_SHPRI3;
|
||
prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
|
||
CPU_CRITICAL_EXIT();
|
||
break;
|
||
|
||
case CPU_INT_SYSTICK: /* SysTick. */
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_SHPRI3;
|
||
prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
|
||
CPU_CRITICAL_EXIT();
|
||
break;
|
||
|
||
|
||
/* ---------------- EXTERNAL INTERRUPT ---------------- */
|
||
default:
|
||
pos_max = CPU_INT_SRC_POS_MAX;
|
||
if (pos < pos_max) { /* See Note #3. */
|
||
group = (pos - 16) / 4;
|
||
nbr = (pos - 16) % 4;
|
||
|
||
CPU_CRITICAL_ENTER();
|
||
temp = CPU_REG_NVIC_PRIO(group);
|
||
CPU_CRITICAL_EXIT();
|
||
|
||
prio = (temp >> (nbr * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
|
||
} else {
|
||
prio = DEF_INT_16S_MIN_VAL;
|
||
}
|
||
break;
|
||
}
|
||
|
||
if (prio >= 0) {
|
||
prio_32 = CPU_RevBits((CPU_INT32U)prio);
|
||
prio = (CPU_INT16S)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
|
||
}
|
||
|
||
return (prio);
|
||
}
|
||
|