396 lines
17 KiB
C
396 lines
17 KiB
C
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/*
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*********************************************************************************************************
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*
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* BOARD SUPPORT PACKAGE
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*
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* Freescale Kinetis K60
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* on the
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*
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* Freescale TWR-K60N512
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* Evaluation Board
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*
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* Filename : bsp.c
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* Version : V1.00
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* Programmer(s) :
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*
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* INCLUDE FILES
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*********************************************************************************************************
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*/
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#define BSP_MODULE
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#include <bsp.h>
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#include <bsp_os.h>
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#include "gd32f4xx.h"
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#include "gd32f4xx_timer.h"
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/*
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*********************************************************************************************************
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* LOCAL GLOBAL VARIABLES
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*********************************************************************************************************
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*/
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static CPU_INT32U BSP_CPU_ClkFreq_MHz;
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/*
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*********************************************************************************************************
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* LOCAL FUNCTION PROTOTYPES
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*********************************************************************************************************
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*/
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//static void BSP_PLL_Init (void);
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static void BSP_Clock_Config(void);
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/*
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*********************************************************************************************************
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* REGISTERS
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*********************************************************************************************************
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*/
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#define DWT_CR *(CPU_REG32 *)0xE0001000 /* Data Watchpoint and Trace (DWT) Control Register */
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#define DWT_CYCCNT *(CPU_REG32 *)0xE0001004 /* Data Watchpoint and Trace (DWT) Cycle Count Register */
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#define DEM_CR *(CPU_REG32 *)0xE000EDFC
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#define DBGMCU_CR *(CPU_REG32 *)0xE0042004 /* ??? Located in the PPB area only in ST ??? */
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/*
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*********************************************************************************************************
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* REGISTER BITS
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*********************************************************************************************************
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*/
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#define DBGMCU_CR_TRACE_IOEN_MASK 0x10 /* ??? Located in the PPB area only in ST ??? */
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#define DBGMCU_CR_TRACE_MODE_ASYNC 0x00 /* ??? Located in the PPB area only in ST ??? */
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#define DBGMCU_CR_TRACE_MODE_SYNC_01 0x40 /* ??? Located in the PPB area only in ST ??? */
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#define DBGMCU_CR_TRACE_MODE_SYNC_02 0x80 /* ??? Located in the PPB area only in ST ??? */
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#define DBGMCU_CR_TRACE_MODE_SYNC_04 0xC0 /* ??? Located in the PPB area only in ST ??? */
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#define DBGMCU_CR_TRACE_MODE_MASK 0xC0 /* ??? Located in the PPB area only in ST ??? */
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#define DEM_CR_TRCENA (1 << 24)
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#define DWT_CR_CYCCNTENA (1 << 0)
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/*
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*********************************************************************************************************
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* LOCAL CONFIGURATION ERRORS
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*********************************************************************************************************
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*/
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#if ((CPU_CFG_TS_TMR_EN != DEF_ENABLED) && \
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(APP_CFG_PROBE_OS_PLUGIN_EN == DEF_ENABLED) && \
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(OS_PROBE_HOOKS_EN == 1))
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#error "CPU_CFG_TS_EN illegally #define'd in 'cpu.h'"
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#error " [MUST be DEF_ENABLED] when "
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#error " using uC/Probe COM modules "
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#endif
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/*
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*********************************************************************************************************
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* BSP_Init()
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*
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* Description : Initialize the Board Support Package (BSP).
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*
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* Argument(s) : none.
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*
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* Return(s) : none.
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*
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* Caller(s) : Application.
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*
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* Note(s) : (1) This function SHOULD be called before any other BSP function is called.
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*
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* (2) CPU instruction / data tracing requires the use of the following pins :
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* (a) (1) Aysynchronous : PB[3]
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* (2) Synchronous 1-bit : PE[3:2]
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* (3) Synchronous 2-bit : PE[4:2]
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* (4) Synchronous 4-bit : PE[6:2]
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*
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* (b) The application may wish to adjust the trace bus width depending on I/O
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* requirements.
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*********************************************************************************************************
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*/
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void BSP_Init (void)
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{
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BSP_Clock_Config();
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}
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/*
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*********************************************************************************************************
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* BSP_Clock_Config()
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*
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* Description : Initialize clock config
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*
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* Argument(s) : none.
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*
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* Return(s) : none.
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*
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* Caller(s) : BSP_Init().
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*
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* Note(s) : none.
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*********************************************************************************************************
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*/
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static void BSP_Clock_Config(void)
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{
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// volatile unsigned int dummy = SYST_CSR;
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DWT_CR |= (CPU_INT32U)0x00000001; /* Enable Cortex-M4's DWT CYCCNT reg. */
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BSP_IntInit(); /* Initialize Interrupts. */
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// systick_clksource_set(SYSTICK_CLKSOURCE_HCLK_DIV8);//SYSTICKʹ<4B><CAB9><EFBFBD>ⲿʱ<E2B2BF><CAB1>Դ
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// BSP_CPU_ClkFreq_MHz = BSP_CPU_ClkFreq() / (CPU_INT32U)1000000;
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// BSP_CPU_ClkFreq_MHz = BSP_CPU_ClkFreq_MHz; /* Surpress compiler warning BSP_CPU_ClkFreq_MHz ... */
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// BSP_PLL_Init();
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} /* ... set and not used. */
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/*
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*********************************************************************************************************
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* BSP_CPU_ClkFreq()
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*
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* Description : Read CPU registers to determine the CPU clock frequency of the chip.
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*
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* Argument(s) : none.
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*
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* Return(s) : The CPU clock frequency, in Hz.
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*
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* Caller(s) : Application.
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*
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* Note(s) : none.
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*********************************************************************************************************
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*/
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CPU_INT32U BSP_CPU_ClkFreq (void)
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{
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CPU_INT32U CLK;
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CLK = 200000000;//rcu_clock_freq_get(CK_SYS);//
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return CLK;
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}
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/*
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*********************************************************************************************************
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* BSP_Tick_Init()
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*
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* Description : Initialize all the peripherals that required OS Tick services (OS initialized)
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*
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* Argument(s) : none.
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*
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* Return(s) : none.
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*
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* Caller(s) : Application.
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*
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* Note(s) : none.
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*********************************************************************************************************
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*/
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void BSP_Tick_Init (void)
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{
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CPU_INT32U cpu_clk_freq;
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CPU_INT32U cnts;
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cpu_clk_freq = BSP_CPU_ClkFreq(); /* Determine SysTick reference freq. */
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#if (OS_VERSION >= 30000u)
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cnts = cpu_clk_freq / (CPU_INT32U)OSCfg_TickRate_Hz; /* Determine nbr SysTick increments. */
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#else
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cnts = cpu_clk_freq / (CPU_INT32U)OS_TICKS_PER_SEC; /* Determine nbr SysTick increments. */
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#endif
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>tick֮<6B><D6AE>ʱ<EFBFBD><CAB1>Ϊ1ms
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OS_CPU_SysTickInit(cnts); /* Init uC/OS periodic time src (SysTick). */
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}
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/*
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*********************************************************************************************************
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* PLL INITIALIZATION
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*
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* Description : This function is called to initialize the PLL.
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*
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* Arguments : none
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*********************************************************************************************************
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*/
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//static void BSP_PLL_Init (void)
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//{
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//#if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
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// CPU_SR cpu_sr;
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//#endif
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//
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// CPU_CRITICAL_ENTER();
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//#ifdef CLK_50M
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// SIM_CLKDIV1 = (uint32_t)0x00110000u;/* Update system prescalers */
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// /* Switch to FBE Mode */
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// /* OSC->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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// //OSC->CR = (u_int8_t)0x00u;
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// MCG_C2 = 0x24;
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// MCG_C1 = 0x9Au;
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// MCG_C4 &= (uint8_t)~(uint8_t)0xE0u;
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// MCG_C5 = (uint8_t)0x00u;
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// MCG_C5 = 0;
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// MCG_C6 = 0;
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// while((MCG_S & 0x2u) == 0u) { /* Check that the oscillator is running */
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// }
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// while((MCG_S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
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// }
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// /* Switch to BLPE Mode */
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// /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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// MCG_C2 = (uint8_t)0x24u;
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//#else
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// MCG_C2 = 0; /* Enable external oscillator */
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//
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// MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3); /* Select external oscilator and Reference Divider and */
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// /* clear IREFS to start ext osc */
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// /* CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0 */
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//
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// while (MCG_S & MCG_S_IREFST_MASK) {}; /* Wait for Reference clock Status bit to clear */
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//
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// /* Wait for clock status bits to show clock */
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// /* source is ext ref clk */
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// while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2) {};
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// //50MHz/25 = 2MHz
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// MCG_C5 = MCG_C5_PRDIV(0x18); /* PLL Ref Divider, PLLCLKEN=0, PLLSTEN=0, PRDIV=0x18 */
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//
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// MCG_C6 = 0; /* Ensure MCG_C6 is at the reset default of 0 */
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//
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// /* Set System Options Dividers = 0x01130000 */
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// SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(BSP_CORE_DIV - 1) | /* Core/System Clock Div by: 1 */
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// SIM_CLKDIV1_OUTDIV2(BSP_BUS_DIV - 1) | /* Peripheral Clock Div by: 2 */
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// SIM_CLKDIV1_OUTDIV3(BSP_FLEXBUS_DIV - 1) | /* FlexBus Clock(FB_CLK) Div by: 2 */
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// SIM_CLKDIV1_OUTDIV4(BSP_FLASH_DIV - 1); /* Flash Clock Div by: 4 */
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//
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// MCG_C5 = DEF_BIT_MASK_08(0x18, MCG_C5_PRDIV_SHIFT); /* PLL Clk Division Factor of: 25 */
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// DEF_BIT_SET_08(MCG_C5, MCG_C5_PLLCLKEN_MASK); /* PLL Clock Enable */
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//
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// /* Set the VCO divider and Selects PLL */
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// MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(BSP_CLOCK_MUL - 24);
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//
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// DEF_BIT_SET_32(SIM_SOPT2, SIM_SOPT2_PLLFLLSEL_MASK); /* Selects MCGPLLCLK Clock for Peripheral Clock */
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//
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// while (!(MCG_S & MCG_S_PLLST_MASK)) {}; /* Wait for PLL status bit to set */
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// while (!(MCG_S & MCG_S_LOCK_MASK)) {}; /* Wait for LOCK bit to set */
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//
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// MCG_C1 &= ~MCG_C1_CLKS_MASK; /* Transition into PEE by setting CLKS to 0 */
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//
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// /* Wait for clock status bits to update */
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// while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3) {};
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//#endif
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// CPU_CRITICAL_EXIT();
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//}
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/*
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*********************************************************************************************************
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* CPU_TS_TmrInit()
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*
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* Description : Initialize & start CPU timestamp timer.
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*
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* Argument(s) : none.
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*
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* Return(s) : Number of left-shifts to scale & return timer as (32-bit) 'CPU_TS' data type
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* (see Note #1a1), if necessary.
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*
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* 0 (see Note #1a2), otherwise.
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*
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* Caller(s) : CPU_TS_Init().
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*
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* Note(s) : (1) (a) Timer count values MUST be scaled & returned via (32-bit) 'CPU_TS' data type.
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*
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* (1) If timer used has less bits, left-shift timer values until the most
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* significant bit of the timer value is shifted into the most
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* significant bit of the return timestamp data type.
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* (2) If timer used has more bits, truncate timer values' higher-order
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* bits greater than the return timestamp data type.
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*
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* (b) Timer SHOULD be an 'up' counter whose values increase with each time count.
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*
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* (c) When applicable, timer period SHOULD be less than the typical measured time
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* but MUST be less than the maximum measured time; otherwise, timer resolution
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* inadequate to measure desired times.
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*
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* See also 'CPU_TS_TmrRd() Note #1'.
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*********************************************************************************************************
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*/
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#if (CPU_CFG_TS_TMR_EN == DEF_ENABLED)
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void CPU_TS_TmrInit (void)
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{
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CPU_INT32U cpu_clk_freq_hz;
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DEM_CR |= (CPU_INT32U)DEM_CR_TRCENA; /* Enable Cortex-M4's DWT CYCCNT reg. */
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DWT_CYCCNT = (CPU_INT32U)0u;
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DWT_CR |= (CPU_INT32U)DWT_CR_CYCCNTENA;
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cpu_clk_freq_hz = BSP_CPU_ClkFreq();
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CPU_TS_TmrFreqSet(cpu_clk_freq_hz);
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}
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#endif
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/*
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*********************************************************************************************************
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* CPU_TS_TmrRd()
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*
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* Description : Get current CPU timestamp timer count value.
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*
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* Argument(s) : none.
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*
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* Return(s) : (32-bit) Timestamp timer count (see Notes #1a & #1b).
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*
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* Caller(s) : CPU_TS_Init(),
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* CPU_TS_UpdateHandler(),
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* CPU_IntDisMeasStart(),
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* CPU_IntDisMeasStop().
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*
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* Note(s) : (1) (a) Timer count values MUST be returned via (32-bit) 'CPU_TS' data type.
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*
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* (1) If timer used has less bits, left-shift timer values until the most
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* significant bit of the timer value is shifted into the most
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* significant bit of the return timestamp data type.
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* (2) If timer used has more bits, truncate timer values' higher-order
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* bits greater than the return timestamp data type.
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*
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* (b) Timer SHOULD be an 'up' counter whose values increase with each time count.
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*
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* (1) If timer is a 'down' counter whose values decrease with each time count,
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* then the returned timer value MUST be ones-complemented.
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*
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* (c) (1) When applicable, the amount of time measured by CPU timestamps is
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* calculated by the following equation :
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*
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* Time measured = Timer period * Number timer counts
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*
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* where
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*
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* Timer period Timer's period in some units of
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* (fractional) seconds
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* Number timer counts Number of timer counts measured
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* Time measured Amount of time measured, in same
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* units of (fractional) seconds
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* as the Timer period
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*
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* (2) Timer period SHOULD be less than the typical measured time but MUST be less
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* than the maximum measured time; otherwise, timer resolution inadequate to
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* measure desired times.
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*********************************************************************************************************
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*/
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#if (CPU_CFG_TS_TMR_EN == DEF_ENABLED)
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CPU_TS CPU_TS_TmrRd (void)
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{
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return ((CPU_TS)DWT_CYCCNT);
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}
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#endif
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