277 lines
15 KiB
C
277 lines
15 KiB
C
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/********************************** (C) COPYRIGHT *******************************
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* File Name : ch32v30x_fsmc.h
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* Author : WCH
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* Version : V1.0.0
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* Date : 2024/03/06
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* Description : This file contains all the functions prototypes for the FSMC
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* firmware library.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#ifndef __CH32V30x_FSMC_H
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#define __CH32V30x_FSMC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "ch32v30x.h"
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/* FSMC Init structure definition */
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typedef struct
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{
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uint32_t FSMC_AddressSetupTime; /* Defines the number of HCLK cycles to configure
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the duration of the address setup time.
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This parameter can be a value between 0 and 0xF.
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@note: It is not used with synchronous NOR Flash memories. */
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uint32_t FSMC_AddressHoldTime; /* Defines the number of HCLK cycles to configure
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the duration of the address hold time.
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This parameter can be a value between 0 and 0xF.
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@note: It is not used with synchronous NOR Flash memories.*/
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uint32_t FSMC_DataSetupTime; /* Defines the number of HCLK cycles to configure
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the duration of the data setup time.
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This parameter can be a value between 0 and 0xFF.
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@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
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uint32_t FSMC_BusTurnAroundDuration; /* Defines the number of HCLK cycles to configure
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the duration of the bus turnaround.
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This parameter can be a value between 0 and 0xF.
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@note: It is only used for multiplexed NOR Flash memories. */
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uint32_t FSMC_CLKDivision; /* Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
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This parameter can be a value between 1 and 0xF.
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@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
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uint32_t FSMC_DataLatency; /* Defines the number of memory clock cycles to issue
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to the memory before getting the first data.
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The value of this parameter depends on the memory type as shown below:
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- It must be set to 0 in case of a CRAM
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- It is don't care in asynchronous NOR, SRAM or ROM accesses
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- It may assume a value between 0 and 0xF in NOR Flash memories
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with synchronous burst mode enable */
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uint32_t FSMC_AccessMode; /* Specifies the asynchronous access mode.
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This parameter can be a value of @ref FSMC_Access_Mode */
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}FSMC_NORSRAMTimingInitTypeDef;
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typedef struct
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{
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uint32_t FSMC_Bank; /* Specifies the NOR/SRAM memory bank that will be used.
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This parameter can be a value of @ref FSMC_NORSRAM_Bank */
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uint32_t FSMC_DataAddressMux; /* Specifies whether the address and data values are
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multiplexed on the databus or not.
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This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
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uint32_t FSMC_MemoryType; /* Specifies the type of external memory attached to
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the corresponding memory bank.
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This parameter can be a value of @ref FSMC_Memory_Type */
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uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width.
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This parameter can be a value of @ref FSMC_Data_Width */
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uint32_t FSMC_BurstAccessMode; /* Enables or disables the burst access mode for Flash memory,
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valid only with synchronous burst Flash memories.
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This parameter can be a value of @ref FSMC_Burst_Access_Mode */
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uint32_t FSMC_AsynchronousWait; /* Enables or disables wait signal during asynchronous transfers,
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valid only with asynchronous Flash memories.
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This parameter can be a value of @ref FSMC_AsynchronousWait */
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uint32_t FSMC_WaitSignalPolarity; /* Specifies the wait signal polarity, valid only when accessing
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the Flash memory in burst mode.
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This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
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uint32_t FSMC_WrapMode; /* Enables or disables the Wrapped burst access mode for Flash
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memory, valid only when accessing Flash memories in burst mode.
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This parameter can be a value of @ref FSMC_Wrap_Mode */
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uint32_t FSMC_WaitSignalActive; /* Specifies if the wait signal is asserted by the memory one
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clock cycle before the wait state or during the wait state,
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valid only when accessing memories in burst mode.
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This parameter can be a value of @ref FSMC_Wait_Timing */
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uint32_t FSMC_WriteOperation; /* Enables or disables the write operation in the selected bank by the FSMC.
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This parameter can be a value of @ref FSMC_Write_Operation */
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uint32_t FSMC_WaitSignal; /* Enables or disables the wait-state insertion via wait
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signal, valid for Flash memory access in burst mode.
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This parameter can be a value of @ref FSMC_Wait_Signal */
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uint32_t FSMC_ExtendedMode; /* Enables or disables the extended mode.
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This parameter can be a value of @ref FSMC_Extended_Mode */
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uint32_t FSMC_WriteBurst; /* Enables or disables the write burst operation.
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This parameter can be a value of @ref FSMC_Write_Burst */
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FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /* Timing Parameters for write and read access if the ExtendedMode is not used*/
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FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /* Timing Parameters for write access if the ExtendedMode is used*/
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}FSMC_NORSRAMInitTypeDef;
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typedef struct
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{
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uint32_t FSMC_SetupTime; /* Defines the number of HCLK cycles to setup address before
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the command assertion for NAND-Flash read or write access
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to common/Attribute or I/O memory space (depending on
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the memory space timing to be configured).
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This parameter can be a value between 0 and 0xFF.*/
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uint32_t FSMC_WaitSetupTime; /* Defines the minimum number of HCLK cycles to assert the
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command for NAND-Flash read or write access to
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common/Attribute or I/O memory space (depending on the
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memory space timing to be configured).
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This parameter can be a number between 0x00 and 0xFF */
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uint32_t FSMC_HoldSetupTime; /* Defines the number of HCLK clock cycles to hold address
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(and data for write access) after the command deassertion
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for NAND-Flash read or write access to common/Attribute
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or I/O memory space (depending on the memory space timing
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to be configured).
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This parameter can be a number between 0x00 and 0xFF */
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uint32_t FSMC_HiZSetupTime; /* Defines the number of HCLK clock cycles during which the
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databus is kept in HiZ after the start of a NAND-Flash
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write access to common/Attribute or I/O memory space (depending
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on the memory space timing to be configured).
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This parameter can be a number between 0x00 and 0xFF */
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}FSMC_NAND_PCCARDTimingInitTypeDef;
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typedef struct
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{
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uint32_t FSMC_Bank; /* Specifies the NAND memory bank that will be used.
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This parameter can be a value of @ref FSMC_NAND_Bank */
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uint32_t FSMC_Waitfeature; /* Enables or disables the Wait feature for the NAND Memory Bank.
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This parameter can be any value of @ref FSMC_Wait_feature */
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uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width.
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This parameter can be any value of @ref FSMC_Data_Width */
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uint32_t FSMC_ECC; /* Enables or disables the ECC computation.
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This parameter can be any value of @ref FSMC_ECC */
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uint32_t FSMC_ECCPageSize; /* Defines the page size for the extended ECC.
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This parameter can be any value of @ref FSMC_ECC_Page_Size */
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uint32_t FSMC_TCLRSetupTime; /* Defines the number of HCLK cycles to configure the
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delay between CLE low and RE low.
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This parameter can be a value between 0 and 0xFF. */
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uint32_t FSMC_TARSetupTime; /* Defines the number of HCLK cycles to configure the
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delay between ALE low and RE low.
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This parameter can be a number between 0x0 and 0xFF */
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FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /* FSMC Common Space Timing */
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FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */
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}FSMC_NANDInitTypeDef;
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/* FSMC_NORSRAM_Bank */
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#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
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/* FSMC_NAND_Bank */
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#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
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/* FSMC_Data_Address_Bus_Multiplexing */
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#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
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#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
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/* FSMC_Memory_Type */
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#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
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#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
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#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
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/* FSMC_Data_Width */
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#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
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#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
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/* FSMC_Burst_Access_Mode */
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#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
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#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
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/* FSMC_AsynchronousWait */
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#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
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#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
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/* FSMC_Wait_Signal_Polarity */
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#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
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#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
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/* FSMC_Wrap_Mode */
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#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
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#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
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/* FSMC_Wait_Timing */
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#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
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#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
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/* FSMC_Write_Operation */
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#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
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#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
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/* FSMC_Wait_Signal */
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#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
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#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
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/* FSMC_Extended_Mode */
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#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
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#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
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/* FSMC_Write_Burst */
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#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
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#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
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/* FSMC_Access_Mode */
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#define FSMC_AccessMode_A ((uint32_t)0x00000000)
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#define FSMC_AccessMode_B ((uint32_t)0x10000000)
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#define FSMC_AccessMode_C ((uint32_t)0x20000000)
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#define FSMC_AccessMode_D ((uint32_t)0x30000000)
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/* FSMC_Wait_feature */
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#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
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#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
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/* FSMC_ECC */
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#define FSMC_ECC_Disable ((uint32_t)0x00000000)
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#define FSMC_ECC_Enable ((uint32_t)0x00000040)
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/* FSMC_ECC_Page_Size */
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#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
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#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
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#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
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#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
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#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
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#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
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#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
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void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
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void FSMC_NANDDeInit(uint32_t FSMC_Bank);
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void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
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void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
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void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
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void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
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void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
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void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
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void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
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uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
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FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
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#ifdef __cplusplus
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}
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#endif
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#endif
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