381 lines
14 KiB
C
381 lines
14 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : ch32v30x_fsmc.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2024/03/06
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* Description : This file provides all the FSMC firmware functions.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include "ch32v30x_fsmc.h"
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#include "ch32v30x_rcc.h"
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/* FSMC BCRx Mask */
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#define BCR_MBKEN_Set ((uint32_t)0x00000001)
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#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
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#define BCR_FACCEN_Set ((uint32_t)0x00000040)
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/* FSMC PCRx Mask */
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#define PCR_PBKEN_Set ((uint32_t)0x00000004)
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#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
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#define PCR_ECCEN_Set ((uint32_t)0x00000040)
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#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
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#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
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/*********************************************************************
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* @fn FSMC_NORSRAMDeInit
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*
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* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
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* reset values.
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*
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* @param FSMC_Bank-
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* FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1.
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*
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* @return none
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*/
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void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
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{
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if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
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{
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FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
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}
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else
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{
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FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
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}
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FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
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FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
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}
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/*********************************************************************
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* @fn FSMC_NANDDeInit
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*
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* @brief Deinitializes the FSMC NAND Banks registers to their default
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* reset values.
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*
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* @param FSMC_Bank -
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* FSMC_Bank2_NAND - FSMC Bank2 NAND.
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*
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* @return none
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*/
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void FSMC_NANDDeInit(uint32_t FSMC_Bank)
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{
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if(FSMC_Bank == FSMC_Bank2_NAND)
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{
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FSMC_Bank2->PCR2 = 0x00000018;
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FSMC_Bank2->SR2 = 0x00000040;
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FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
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FSMC_Bank2->PATT2 = 0xFCFCFCFC;
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}
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}
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/*********************************************************************
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* @fn FSMC_NORSRAMInit
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*
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* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
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* parameters in the FSMC_NORSRAMInitStruct.
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*
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* @param SMC_NORSRAMInitStruct:pointer to a FSMC_NORSRAMInitTypeDef
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* structure that contains the configuration information for the FSMC NOR/SRAM
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* specified Banks.
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*
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* @return none
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*/
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void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
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{
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FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
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(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
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FSMC_NORSRAMInitStruct->FSMC_MemoryType |
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FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
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FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
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FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
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FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
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FSMC_NORSRAMInitStruct->FSMC_WrapMode |
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FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
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FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
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FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
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FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
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FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
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if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
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{
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FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
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}
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FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank + 1] =
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(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
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if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
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{
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FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
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(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
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(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4) |
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(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
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}
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else
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{
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FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
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}
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}
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/*********************************************************************
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* @fn FSMC_NANDInit
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*
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* @brief Initializes the FSMC NAND Banks according to the specified
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* parameters in the FSMC_NANDInitStruct.
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*
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* @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef
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* structure that contains the configuration information for the FSMC
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* NAND specified Banks.
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*
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* @return none
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*/
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void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
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{
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uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
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tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
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PCR_MemoryType_NAND |
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FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
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FSMC_NANDInitStruct->FSMC_ECC |
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FSMC_NANDInitStruct->FSMC_ECCPageSize |
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(FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9) |
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(FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
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tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
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(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
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(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
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(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
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tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
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(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
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(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
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(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
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if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
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{
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FSMC_Bank2->PCR2 = tmppcr;
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FSMC_Bank2->PMEM2 = tmppmem;
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FSMC_Bank2->PATT2 = tmppatt;
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}
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}
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/*********************************************************************
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* @fn FSMC_NORSRAMStructInit
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*
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* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
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*
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* @param FSMC_NORSRAMInitStruct - pointer to a FSMC_NORSRAMInitTypeDef
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* structure which will be initialized.
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*
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* @return none
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*/
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void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
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{
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FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
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FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
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FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
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FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
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FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
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FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
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FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
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FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
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FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
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}
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/*********************************************************************
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* @fn FSMC_NANDStructInit
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*
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* @brief Fills each FSMC_NANDInitStruct member with its default value.
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*
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* @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef
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* structure which will be initialized.
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*
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* @return none
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*/
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void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
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{
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FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
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FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
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FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
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FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
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FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
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FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
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FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
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FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
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FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
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FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
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FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
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FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
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FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
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FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
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FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
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}
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/*********************************************************************
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* @fn FSMC_NORSRAMCmd
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*
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* @brief Enables or disables the specified NOR/SRAM Memory Bank.
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*
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* @param FSMC_Bank - specifies the FSMC Bank to be used
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* FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1
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* FSMC_Bank1_NORSRAM2 - FSMC Bank1 NOR/SRAM2
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* FSMC_Bank1_NORSRAM3 - FSMC Bank1 NOR/SRAM3
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* FSMC_Bank1_NORSRAM4 - FSMC Bank1 NOR/SRAM4
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* NewState:ENABLE or DISABLE.
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*
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* @return none
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*/
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void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
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{
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if(NewState != DISABLE)
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{
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FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
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}
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else
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{
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FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
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}
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}
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/*********************************************************************
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* @fn FSMC_NANDCmd
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*
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* @brief Enables or disables the specified NAND Memory Bank.
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*
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* @param FSMC_Bank - specifies the FSMC Bank to be used
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* FSMC_Bank2_NAND - FSMC Bank2 NAND
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* NewStat - ENABLE or DISABLE.
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*
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* @return none
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*/
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void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
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{
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if(NewState != DISABLE)
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{
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if(FSMC_Bank == FSMC_Bank2_NAND)
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{
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FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
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}
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}
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else
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{
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if(FSMC_Bank == FSMC_Bank2_NAND)
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{
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FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
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}
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}
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}
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/*********************************************************************
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* @fn FSMC_NANDECCCmd
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*
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* @brief Enables or disables the FSMC NAND ECC feature.
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*
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* @param FSMC_Bank - specifies the FSMC Bank to be used
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* FSMC_Bank2_NAND - FSMC Bank2 NAND
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* NewState - ENABLE or DISABLE.
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*
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* @return none
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*/
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void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
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{
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if(NewState != DISABLE)
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{
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if(FSMC_Bank == FSMC_Bank2_NAND)
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{
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FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
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}
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}
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else
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{
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if(FSMC_Bank == FSMC_Bank2_NAND)
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{
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FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
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}
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}
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}
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/*********************************************************************
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* @fn FSMC_GetECC
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*
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* @brief Returns the error correction code register value.
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*
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* @param FSMC_Bank - specifies the FSMC Bank to be used
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* FSMC_Bank2_NAND - FSMC Bank2 NAND
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* NewState - ENABLE or DISABLE.
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*
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* @return eccval - The Error Correction Code (ECC) value.
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*/
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uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
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{
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uint32_t eccval = 0x00000000;
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if(FSMC_Bank == FSMC_Bank2_NAND)
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{
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eccval = FSMC_Bank2->ECCR2;
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}
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return (eccval);
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}
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/*********************************************************************
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* @fn FSMC_GetFlagStatus
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*
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* @brief Checks whether the specified FSMC flag is set or not.
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*
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* @param FSMC_Bank - specifies the FSMC Bank to be used
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* FSMC_Bank2_NAND - FSMC Bank2 NAND
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* FSMC_FLAG - specifies the flag to check.
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* FSMC_FLAG_FEMPT - Fifo empty Flag.
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* NewState - ENABLE or DISABLE.
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*
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* @return FlagStatus - The new state of FSMC_FLAG (SET or RESET).
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*/
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FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
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{
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FlagStatus bitstatus = RESET;
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uint32_t tmpsr = 0x00000000;
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if(FSMC_Bank == FSMC_Bank2_NAND)
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{
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tmpsr = FSMC_Bank2->SR2;
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}
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if((tmpsr & FSMC_FLAG) != (uint16_t)RESET)
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{
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bitstatus = SET;
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}
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else
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{
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bitstatus = RESET;
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}
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return bitstatus;
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}
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