
/*
*********************************************************************************************************
*
*                                        BOARD SUPPORT PACKAGE
*
*                                        Freescale Kinetis K60
*                                               on the
*
*                                        Freescale TWR-K60N512
*                                          Evaluation Board
*
* Filename      : bsp.c
* Version       : V1.00
* Programmer(s) :
*
*********************************************************************************************************
*/

/*
*********************************************************************************************************
*                                             INCLUDE FILES
*********************************************************************************************************
*/

#define   BSP_MODULE
#include  <bsp.h>
#include  <bsp_os.h>
#include "gd32f4xx.h"
#include "gd32f4xx_timer.h"
/*
*********************************************************************************************************
*                                       LOCAL GLOBAL VARIABLES
*********************************************************************************************************
*/

static  CPU_INT32U  BSP_CPU_ClkFreq_MHz;

/*
*********************************************************************************************************
*                                      LOCAL FUNCTION PROTOTYPES
*********************************************************************************************************
*/

//static  void  BSP_PLL_Init   (void);
static  void  BSP_Clock_Config(void);
/*
*********************************************************************************************************
*                                             REGISTERS
*********************************************************************************************************
*/

#define  DWT_CR      *(CPU_REG32 *)0xE0001000                   /* Data Watchpoint and Trace (DWT) Control Register     */
#define  DWT_CYCCNT  *(CPU_REG32 *)0xE0001004                   /* Data Watchpoint and Trace (DWT) Cycle Count Register */
#define  DEM_CR      *(CPU_REG32 *)0xE000EDFC
#define  DBGMCU_CR   *(CPU_REG32 *)0xE0042004                   /* ??? Located in the PPB area only in ST           ??? */

/*
*********************************************************************************************************
*                                            REGISTER BITS
*********************************************************************************************************
*/

#define  DBGMCU_CR_TRACE_IOEN_MASK       0x10                   /* ??? Located in the PPB area only in ST           ??? */
#define  DBGMCU_CR_TRACE_MODE_ASYNC      0x00                   /* ??? Located in the PPB area only in ST           ??? */
#define  DBGMCU_CR_TRACE_MODE_SYNC_01    0x40                   /* ??? Located in the PPB area only in ST           ??? */
#define  DBGMCU_CR_TRACE_MODE_SYNC_02    0x80                   /* ??? Located in the PPB area only in ST           ??? */
#define  DBGMCU_CR_TRACE_MODE_SYNC_04    0xC0                   /* ??? Located in the PPB area only in ST           ??? */
#define  DBGMCU_CR_TRACE_MODE_MASK       0xC0                   /* ??? Located in the PPB area only in ST           ??? */

#define  DEM_CR_TRCENA                   (1 << 24)

#define  DWT_CR_CYCCNTENA                (1 <<  0)


/*
*********************************************************************************************************
*                                     LOCAL CONFIGURATION ERRORS
*********************************************************************************************************
*/

#if ((CPU_CFG_TS_TMR_EN          != DEF_ENABLED) && \
     (APP_CFG_PROBE_OS_PLUGIN_EN == DEF_ENABLED) && \
     (OS_PROBE_HOOKS_EN          == 1))
#error  "CPU_CFG_TS_EN                  illegally #define'd in 'cpu.h'"
#error  "                              [MUST be  DEF_ENABLED] when    "
#error  "                               using uC/Probe COM modules    "
#endif

/*
*********************************************************************************************************
*                                               BSP_Init()
*
* Description : Initialize the Board Support Package (BSP).
*
* Argument(s) : none.
*
* Return(s)   : none.
*
* Caller(s)   : Application.
*
* Note(s)     : (1) This function SHOULD be called before any other BSP function is called.
*
*               (2) CPU instruction / data tracing requires the use of the following pins :
*                   (a) (1) Aysynchronous     :  PB[3]
*                       (2) Synchronous 1-bit :  PE[3:2]
*                       (3) Synchronous 2-bit :  PE[4:2]
*                       (4) Synchronous 4-bit :  PE[6:2]
*
*                   (b) The application may wish to adjust the trace bus width depending on I/O
*                       requirements.
*********************************************************************************************************
*/


void  BSP_Init (void)
{      
    BSP_Clock_Config();                                                            
    
}

/*
*********************************************************************************************************
*                                              BSP_Clock_Config()
*
* Description : Initialize clock config
*
* Argument(s) : none.
*
* Return(s)   : none.
*
* Caller(s)   : BSP_Init().
*
* Note(s)     : none.
*********************************************************************************************************
*/
static void BSP_Clock_Config(void)
{
//   volatile unsigned int dummy = SYST_CSR;      

   DWT_CR |= (CPU_INT32U)0x00000001;                           /* Enable Cortex-M4's DWT CYCCNT reg.                   */

   BSP_IntInit();                                              /* Initialize Interrupts.                               */

//    systick_clksource_set(SYSTICK_CLKSOURCE_HCLK_DIV8);//SYSTICK使用外部时钟源	
   
//    BSP_CPU_ClkFreq_MHz = BSP_CPU_ClkFreq() / (CPU_INT32U)1000000;


//    BSP_CPU_ClkFreq_MHz = BSP_CPU_ClkFreq_MHz;                  /* Surpress compiler warning BSP_CPU_ClkFreq_MHz    ... */

//    BSP_PLL_Init();
}                                                                /* ... set and not used.                                */

/*
*********************************************************************************************************
*                                            BSP_CPU_ClkFreq()
*
* Description : Read CPU registers to determine the CPU clock frequency of the chip.
*
* Argument(s) : none.
*
* Return(s)   : The CPU clock frequency, in Hz.
*
* Caller(s)   : Application.
*
* Note(s)     : none.
*********************************************************************************************************
*/

CPU_INT32U  BSP_CPU_ClkFreq (void)
{
  CPU_INT32U CLK;
  CLK = 200000000;//rcu_clock_freq_get(CK_SYS);//
  return CLK;
}

/*
*********************************************************************************************************
*                                            BSP_Tick_Init()
*
* Description : Initialize all the peripherals that required OS Tick services (OS initialized)
*
* Argument(s) : none.
*
* Return(s)   : none.
*
* Caller(s)   : Application.
*
* Note(s)     : none.
*********************************************************************************************************
*/

void BSP_Tick_Init (void)
{
    CPU_INT32U  cpu_clk_freq;
    CPU_INT32U  cnts;

    cpu_clk_freq = BSP_CPU_ClkFreq();                           /* Determine SysTick reference freq.                    */

#if (OS_VERSION >= 30000u)
    cnts  = cpu_clk_freq / (CPU_INT32U)OSCfg_TickRate_Hz;       /* Determine nbr SysTick increments.                    */
#else
    cnts  = cpu_clk_freq / (CPU_INT32U)OS_TICKS_PER_SEC;        /* Determine nbr SysTick increments.                    */
#endif
    //设置两个tick之间时间为1ms
    OS_CPU_SysTickInit(cnts);                                   /* Init uC/OS periodic time src (SysTick).              */
}

/*
*********************************************************************************************************
*                                         PLL INITIALIZATION
*
* Description : This function is called to initialize the PLL.
*
* Arguments   : none
*********************************************************************************************************
*/

//static  void  BSP_PLL_Init (void)
//{
//#if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
//    CPU_SR  cpu_sr;
//#endif
//
//    CPU_CRITICAL_ENTER();
//#ifdef CLK_50M
//    SIM_CLKDIV1 = (uint32_t)0x00110000u;/* Update system prescalers */
//    /* Switch to FBE Mode */
//    /* OSC->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
//    //OSC->CR = (u_int8_t)0x00u;
//    MCG_C2 = 0x24;                                                
//    MCG_C1 = 0x9Au;
//    MCG_C4 &= (uint8_t)~(uint8_t)0xE0u; 
//    MCG_C5 = (uint8_t)0x00u;
//    MCG_C5 = 0;
//    MCG_C6 = 0;
//    while((MCG_S & 0x2u) == 0u) { /* Check that the oscillator is running */
//    }
//    while((MCG_S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
//    }
//   /* Switch to BLPE Mode */
//   /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
//   MCG_C2 = (uint8_t)0x24u;
//#else    
//    MCG_C2 = 0;                                                 /* Enable external oscillator                           */
//
//    MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);                  /* Select external oscilator and Reference Divider and  */
//                                                                /* clear IREFS to start ext osc                         */
//                                                                /* CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0      */
//
//    while (MCG_S & MCG_S_IREFST_MASK) {};                       /* Wait for Reference clock Status bit to clear         */
//
//                                                                /* Wait for clock status bits to show clock             */
//                                                                /* source is ext ref clk                                */
//    while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2) {};
//    //50MHz/25 = 2MHz
//    MCG_C5 = MCG_C5_PRDIV(0x18);                                /* PLL Ref Divider, PLLCLKEN=0, PLLSTEN=0, PRDIV=0x18   */
//
//    MCG_C6 = 0;                                                 /* Ensure MCG_C6 is at the reset default of 0           */
//
//                                                                /* Set System Options Dividers = 0x01130000             */
//    SIM_CLKDIV1 =   SIM_CLKDIV1_OUTDIV1(BSP_CORE_DIV - 1)    |  /*     Core/System Clock        Div by: 1               */
//                    SIM_CLKDIV1_OUTDIV2(BSP_BUS_DIV - 1)     |  /*     Peripheral Clock         Div by: 2               */
//                    SIM_CLKDIV1_OUTDIV3(BSP_FLEXBUS_DIV - 1) |  /*     FlexBus Clock(FB_CLK)    Div by: 2               */
//                    SIM_CLKDIV1_OUTDIV4(BSP_FLASH_DIV - 1);     /*     Flash Clock              Div by: 4               */
//
//    MCG_C5 = DEF_BIT_MASK_08(0x18, MCG_C5_PRDIV_SHIFT);         /* PLL Clk Division Factor of: 25                       */
//    DEF_BIT_SET_08(MCG_C5, MCG_C5_PLLCLKEN_MASK);               /* PLL Clock Enable                                     */
//
//                                                                /* Set the VCO divider and Selects PLL                  */
//    MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(BSP_CLOCK_MUL - 24);
//
//    DEF_BIT_SET_32(SIM_SOPT2, SIM_SOPT2_PLLFLLSEL_MASK);        /* Selects MCGPLLCLK Clock for Peripheral Clock         */
//
//    while (!(MCG_S & MCG_S_PLLST_MASK)) {};                     /* Wait for PLL status bit to set                       */
//    while (!(MCG_S & MCG_S_LOCK_MASK)) {};                      /* Wait for LOCK bit to set                             */
//
//    MCG_C1 &= ~MCG_C1_CLKS_MASK;                                /* Transition into PEE by setting CLKS to 0             */
//
//                                                                /* Wait for clock status bits to update                 */
//    while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3) {};
//#endif
//    CPU_CRITICAL_EXIT();
//}


/*
*********************************************************************************************************
*                                          CPU_TS_TmrInit()
*
* Description : Initialize & start CPU timestamp timer.
*
* Argument(s) : none.
*
* Return(s)   : Number of left-shifts to scale & return timer as (32-bit) 'CPU_TS' data type
*                 (see Note #1a1), if necessary.
*
*               0 (see Note #1a2), otherwise.
*
* Caller(s)   : CPU_TS_Init().
*
* Note(s)     : (1) (a) Timer count values MUST be scaled & returned via (32-bit) 'CPU_TS' data type.
*
*                       (1) If timer used has less bits, left-shift timer values until the most
*                           significant bit of the timer value is shifted into         the most
*                           significant bit of the return timestamp data type.
*                       (2) If timer used has more bits, truncate   timer values' higher-order
*                           bits greater than  the return timestamp data type.
*
*                   (b) Timer SHOULD be an 'up'  counter whose values increase with each time count.
*
*                   (c) When applicable, timer period SHOULD be less than the typical measured time
*                       but MUST be less than the maximum measured time; otherwise, timer resolution
*                       inadequate to measure desired times.
*
*                   See also 'CPU_TS_TmrRd()  Note #1'.
*********************************************************************************************************
*/

#if (CPU_CFG_TS_TMR_EN == DEF_ENABLED)
void  CPU_TS_TmrInit (void)
{
    CPU_INT32U  cpu_clk_freq_hz;


    DEM_CR         |= (CPU_INT32U)DEM_CR_TRCENA;                /* Enable Cortex-M4's DWT CYCCNT reg.                   */
    DWT_CYCCNT      = (CPU_INT32U)0u;
    DWT_CR         |= (CPU_INT32U)DWT_CR_CYCCNTENA;

    cpu_clk_freq_hz = BSP_CPU_ClkFreq();
    CPU_TS_TmrFreqSet(cpu_clk_freq_hz);
}
#endif


/*
*********************************************************************************************************
*                                           CPU_TS_TmrRd()
*
* Description : Get current CPU timestamp timer count value.
*
* Argument(s) : none.
*
* Return(s)   : (32-bit) Timestamp timer count (see Notes #1a & #1b).
*
* Caller(s)   : CPU_TS_Init(),
*               CPU_TS_UpdateHandler(),
*               CPU_IntDisMeasStart(),
*               CPU_IntDisMeasStop().
*
* Note(s)     : (1) (a) Timer count values MUST be returned via (32-bit) 'CPU_TS' data type.
*
*                       (1) If timer used has less bits, left-shift timer values until the most
*                           significant bit of the timer value is shifted into         the most
*                           significant bit of the return timestamp data type.
*                       (2) If timer used has more bits, truncate   timer values' higher-order
*                           bits greater than  the return timestamp data type.
*
*                   (b) Timer SHOULD be an 'up'  counter whose values increase with each time count.
*
*                       (1) If timer is a 'down' counter whose values decrease with each time count,
*                           then the returned timer value MUST be ones-complemented.
*
*                   (c) (1) When applicable, the amount of time measured by CPU timestamps is
*                           calculated by the following equation :
*
*                               Time measured  =  Timer period  *  Number timer counts
*
*                                   where
*
*                                       Timer period            Timer's period in some units of
*                                                                   (fractional) seconds
*                                       Number timer counts     Number of timer counts measured
*                                       Time measured           Amount of time measured, in same
*                                                                   units of (fractional) seconds
*                                                                   as the Timer period
*
*                       (2) Timer period SHOULD be less than the typical measured time but MUST be less
*                           than the maximum measured time; otherwise, timer resolution inadequate to
*                           measure desired times.
*********************************************************************************************************
*/

#if (CPU_CFG_TS_TMR_EN == DEF_ENABLED)
CPU_TS  CPU_TS_TmrRd (void)
{
    return ((CPU_TS)DWT_CYCCNT);
}
#endif





